Advanced Packaging — Yicheng Yang

At a glance

Winners

TSMCEV Group (EVG)Besi (with a caveat)Front-end tool & process incumbents (AMAT, TEL, Disco, ACM)Intel (packaging franchise)ASMPT & Kulicke and Soffa

Bottlenecks

TSV formation — the deep-etch/CVD/ECD sequence bottlenecking both HBM and CoWoS output; customers switch to CoWoS-R partly to dodge interposer TSV cost.D2W bonder throughput-vs-accuracy: 2,000 dies/hr claims collapse below 1,000 at 1µm accuracy, while 3µm pitches demand <0.5µm placement for 98% yield.ISO 1-3 cleanroom + front-end toolset capacity — hybrid-bonding supply can't come from OSAT brownfield; it must be built to fab standards.KGD testing without wrecking the bond surface: probe marks violate the 1nm roughness spec, forcing extra CMP passes and constraining wafer-sort strategies.

Risks

The chiplet cost fallacy cuts both ways: reticle utilization and Emerald Rapids show packaging-intensive designs can lose to monolithic — advanced-packaging TAM is not a one-way ratchet.Hybrid-bonding adoption slippage: through early 2024 AMD remained the only D2W logic adopter; the cost barrier is real and each pitch shrink resets the yield learning curve.OSAT disintermediation: as value migrates to fab-grade processes, ASE/Amkor risk being stuck with commoditizing bump/fanout while foundries take the premium layers.Reliability/CTE physics: warpage and thermal cycling killed early interposer products (AMD Fiji); chip-first fanout still burns known-good dies on packaging yield; every new hybrid substrate re-opens these failure modes.

Catalysts

Hybrid bonding breaking out beyond V-Cache: MI300-class D2W volume, SK Hynix W2W for 16-hi HBM, and TSMC N2-era customer-specific SoIC flows would inflect the whole tool chain.CoWoS/HBM capacity expansions and the CoWoS-R/R+ substitution wave (45x-reticle roadmap) as AI package sizes balloon into the kilowatt range.Intel's packaging ramp: $7B Malaysia facility, EMR/Meteor-Arrow Lake EMIB+Foveros volume, and TCB fleet doubling — a read-through for ASMPT/K&S/Besi order books.Panel-level fanout and coreless ABF hitting cost crossover; co-packaged optics / optical interposers (Lightmatter Passage, Ayar Labs) getting a first volume design win.EMIB-T (bridge + through-bridge TSVs) and organic-RDL custom HBM maturing at ECTC 2026 as alternatives to reticle-limited silicon interposers.

Overview

SemiAnalysis's throughline across this bucket: transistor density doubled every ~2 years while chip IO data rates doubled only every ~4, so designs became pad-limited just as cost-per-transistor stopped falling (N7 ~$9.5k vs N5 ~$16k wafers). Chiplets fix yield but not IO — and aren't even always cheaper (reticle utilization can inflate wafer cost 26%; Intel re-aggregated Emerald Rapids back to 2 big dies). The escape is packaging density: from 150-200µm flip-chip bumps to fanout (~8x IO density), 2.5D interposers (~16x), 36µm micro-bump 3D (31x), 17µm hybrid-bonded V-Cache (138x) and Sony's 6.3µm image sensors (567x). Hybrid bonding — bumpless Cu-Cu at sub-10µm pitch with a roadmap to hundreds of nanometers — is 'the most transformative innovation since EUV', but it demands ISO 1-3 cleanrooms and fab tools (CVD/PVD/ECD/CMP), structurally excluding OSATs and handing the market to TSMC, Intel and front-end equipment vendors. The battlegrounds: wafer-on-wafer (sub-50nm alignment, but no known-good-die sorting) vs die-to-wafer (KGD, but dirty and slow — Besi's claimed 2,000 dies/hr collapses below 1,000 at 1µm accuracy); Intel's curious ~300-tool TCB fleet; fanout/bridges/coreless ABF eating silicon interposers from below; and hyperscalers (Graviton3, Dojo, AmpereOne) using packaging to commoditize incumbents' CPUs.

Positioning: Who Wins and Why

TSMC — Owns every rung of the ladder — InFO (Apple), CoWoS-S/R/R+ (Nvidia, roadmap to 45x reticle), SoIC CoW (AMD V-Cache/MI300) and SoIC WoW (Graphcore) — and hybrid bonding's fab-grade requirements pull even more of the package into its fabs. Vanguard customers de-risk each new flow before volume.

EV Group (EVG) — Dominant in W2W fusion/hybrid bonding with patented SmartView alignment (sub-50nm). W2W is the mature, high-volume path (every Sony CIS, YMTC NAND, Graphcore Bow) and the likely vehicle for 16-hi HBM hybrid bonding.

Besi (with a caveat) — De-facto D2W hybrid-bonding bonder at TSMC (8800 Ultra picks and places every V-Cache die). But SemiAnalysis repeatedly flags real accuracy ~0.5µm at half rated throughput and holds 'a very non-consensus view' — the D2W moat may be narrower than the consensus multiple assumes, especially if collective/self-assembly flows mature.

Front-end tool & process incumbents (AMAT, TEL, Disco, ACM) — Hybrid bonding converts packaging capex into front-end tool spend: PECVD, PVD/ECD, precision CMP, plasma dicing, megasonic cleans. TEL won TSMC's W2W bonder socket (the Graphcore flow); Disco leads clean dicing and 'has more than tripled' since SemiAnalysis's write-up.

Intel (packaging franchise) — The one area where Intel is genuinely differentiated: a decade of co-developed TCB (~300 tools, $7B Malaysia doubling), EMIB bridges at 55µm ramping in every Xeon, Foveros/Omni bringing 36µm 3D to mass-market client chips, and QMC research pointing at reconstituted W2W. Packaging is Intel's credible foundry hook.

ASMPT & Kulicke and Soffa — The TCB order book rises structurally with HBM stack heights (30µm dies leave no alternative) and with OSAT/mobile adoption; each of the three TCB vendors 'excels in different areas' and owns a defensible niche.

Key Data

Metric	Value	Note
Transistor vs IO scaling	Transistor density 2x every 2 years; IO data rates 2x every 4 years	The decades-long divergence that created pad-limited designs and the entire advanced-packaging market.
Advanced packaging definition	Bump pitch < 100µm (standard flip chip = 150-200µm, essentially unchanged 2000→2021)	SemiAnalysis's line in the sand; tool vendors calling all flip chip 'advanced' are ignored.
IO density ladder vs standard flip chip	Fanout (90-60µm) ~8x → 2.5D (55-50µm) ~16x → 3D µbump (36µm) 31x → HB V-Cache (17µm TSV) 138x → Sony CIS (6.3µm) 567x	Each packaging generation is a step-function in interconnect density; hybrid bonding roadmap extends to 100s of nm. Multipliers are all relative to standard flip chip (150-200µm), with the baseline not uniform across rungs.
Wafer prices, N7 vs N5	~$9,500 (N7) vs ~$16,000 (N5)	Evidence cost-per-transistor is rising; SemiAnalysis's rebuttal to Morgan Stanley's TSMC downgrade.
Hybrid bonding particle sensitivity	A 1µm-tall particle → ~10mm-diameter bond void	Why HB requires ISO 3/class 1 cleanrooms or better (TSMC/Intel going ISO 2-1) — and why OSATs are locked out.
HB surface-roughness spec	≤0.5nm dielectric, ≤1nm copper pads; Cu recessed ~5nm pre-anneal	Maintained through the whole flow via multi-pass CMP; even wafer-sort probing must be polished out afterwards.
Bond alignment accuracy, W2W vs D2W	W2W sub-50nm; Besi 8800 Ultra claims <200nm but 'more like 0.5µm with wide variance' at half rated throughput	The spec-vs-reality gap behind SemiAnalysis's non-consensus BESI view.
TSMC SoIC gen-4 (3µm pitch) bond yield	100,000 pads/mm2; 98% yield <0.5µm misalignment, 60% beyond 1µm	Defines the accuracy bar every D2W bonder must clear as pitches shrink from 9µm to 3µm.
D2W bonder throughput cliff	Claimed 2,000 dies/hr → <1,000/hr at 1µm accuracy	Throughput-accuracy tradeoff is the central battle of the hybrid-bonding tool market.
TCB vs flip-chip tool economics	TCB: ~$1.25M, 500-1,000 dies/hr. Flip-chip placer: ~$450k, 3,000-10,000 dies/hr	6-20x throughput gap at ~1/3 the price — yet Intel chooses TCB for yield/reliability in high-margin parts.
Intel TCB fleet	~300 tools, doubling with the $7B Malaysia packaging facility	Far exceeds Intel's advanced-packaging needs; a decade of co-development = a hard-to-copy moat.
Reticle utilization cost penalty	Bad field tiling → 1.875x scan steps → wafer repriced $17,000 → $21,364 (litho ≈ 1/3 of wafer cost)	Chiplet silicon saving collapses $136 → $26 ($541 vs $567); likely flips negative once packaging costs are added.
Emerald Rapids re-aggregation	4 dies → 2; chiplet interface 16.2% → 5.8% of die area; EMIBs 10 → 3; core-area utilization 50.7% → 62.7%; but 37 → 34 CPUs/wafer	Fewer chiplets bought back area yet still raised cost per CPU — big rectangles tile round wafers badly.
Graphcore Bow uplift from W2W hybrid bonding	+40% clocks (1.325 → 1.85GHz), +16% perf/W, same node/architecture/cost; W2W TSV pitch ~1/10th of chip-on-wafer	First 3D W2W-bonded logic processor; the top die is just deep-trench capacitors for power delivery.
AMD 3D V-Cache production reality	17µm production pitch (TechInsights) vs the 9µm AMD used in marketing comparisons; 5 bond steps per chip; a 5th structural support die on top	First and (through early 2024) only D2W hybrid-bonded logic product; claimed 3x interconnect efficiency and 16x density vs 36µm µbump.
HBM die thinning	30µm per die in SK Hynix 12-hi HBM3 (< half a human hair)	Forces TCB today; SK Hynix presented W2W hybrid bonding for 16-hi HBM at ECTC 2022; TSV formation bottlenecks HBM & CoWoS.
Substrate/RDL line-space race (L/S)	ABF 10µm → Cisco coreless 6µm → Unimicron coreless 3µm (panel) \| EMIB 5µm → 2µm \| advanced fanout 2µm \| Amkor SLIM 0.4µm / ASE NTI 0.5µm (first layer)	Cheaper organic technologies keep climbing into silicon-interposer territory; CoWoS-R roadmap = 45x reticle vs CoWoS-S 4x.
Samsung's packaging-overhead study (450mm2 HPC design)	vs monolithic: MCM +2.1% power/+5.6% area; 2.5D +1.1%/+2.4%; 3D +0.04% power/+2.4% area	Ideal-case numbers, but they quantify why 3D stacking is the endgame: near-zero power overhead.
Intel EMIB-T (bridge + backside-power TSVs)	36/35µm bump pitch on 2x reticle (+65% bump density vs 45µm Granite Rapids); 25µm in test; through-bridge TSVs cut DC IR-drop 68-80%; ~67% eye width at 12 Gb/s HBM4E	EMIB with backside power TSVs, disclosed at ECTC 2026 (SemiAnalysis).
Marvell custom-HBM packaging	Organic RDL instead of silicon interposer; HBM interposer channel shortened 6.5mm → 1.5mm	Substrate-side path that eases CoWoS-S interposer dependence (ECTC 2026, SemiAnalysis).

Key Theses

1. The root cause: IO scaling runs at half the pace of transistor scaling, so the industry hit a pad-limited wall that only packaging can fix.

Density of real chips grew ~2x/3yr against 2x/2yr transistor density partly because IO, power delivery and SRAM stalled. Flip chip stayed ~150-200µm from 2000 to 2021; AMD's move to 130µm bought just 2.35x more IO against orders-of-magnitude more transistors. Designers first coped by bloating dies with cache (Infinity Cache cut a 384-bit GDDR6 bus to 256-bit) — but Nvidia and Intel have been at reticle limit for 5+ years. Packaging density is the only lever left.

“Moore's law has had the industry increasing transistor densities roughly 2x every 2 years, but the rate of IO data rates have only been 2x every 4 years.”— Advanced Packaging Part 1 – Pad Limited Designs (2021-12-15), SemiAnalysis

2. Cost per transistor is rising, not falling — the deflationary engine of the industry broke at 7nm/5nm, and that reversal is what funds the packaging renaissance.

AMD's own data shows cost per yielded mm2 inflecting sharply at 7nm/5nm. SemiAnalysis's receipts: N7 wafers ~$9,500 vs N5 ~$16,000 while Apple's die size barely fell — and they mock Morgan Stanley's TSMC downgrade chart claiming 5nm transistors were cheaper than 7nm. When shrink no longer buys cost, heterogeneous integration and packaging become the only route to more capability per dollar.

“Cost per transistor stalled with the introduction of FinFET nodes, 7nm completely plateaued, and with 5nm they are higher than ever before.”— Advanced Packaging Part 1 – Pad Limited Designs (2021-12-15), SemiAnalysis

3. Hybrid bonding is the biggest paradigm shift in packaging since flip chip — SemiAnalysis rates it above EUV in design impact.

Everything from wire bond to TCB still uses solder bumps, which bottom out around 20µm pitch. Hybrid bonding is bumpless Cu-Cu: sub-10µm today, a roadmap into the hundreds of nanometers, lower resistance, latency 'in some cases shorter than global routing on chip'. It reshapes IP ecosystems, cell design and manufacturing flows — designers must start thinking in 3D. In 2024 it shipped only in AMD chips, CMOS sensors and some 3D NAND, which is exactly the opportunity.

“Hybrid bonding is going to be the most transformative innovation to semiconductor manufacturing since EUV.”— Hybrid Bonding Process Flow - Advanced Packaging Part 5 (2024-02-09), SemiAnalysis

4. Hybrid bonding is a front-end process — its cleanliness physics structurally lock OSATs out and hand packaging to TSMC, Intel and fab-tool vendors.

A particle just 1µm tall creates a 10mm bond void; surface roughness must stay within 0.5nm (dielectric) / 1nm (copper). That demands ISO 3 / class 1 cleanrooms or better — TSMC and Intel are going to ISO 2 or ISO 1 — plus fab tools OSATs barely own: CVD, PVD, ECD, CMP, plasma activation, megasonic cleans. ASE and Amkor would need to build new fab-grade cleanrooms; TSMC and Intel just reuse old fabs. The margin pool migrates accordingly.

“It is very difficult for OSATs to pursue hybrid bonding given this upgrade in cleanliness requirement.”— Hybrid Bonding Process Flow - Advanced Packaging Part 5 (2024-02-09), SemiAnalysis

5. W2W vs D2W is decided by one variable: known good die. W2W is cheaper and more accurate until die size and yield losses flip the curve.

W2W separates alignment from bonding, achieves sub-50nm accuracy, and dominates high-yield small-die volume (CIS, NAND). But it cannot sort dies, so defective dies get bonded to good ones — its cost curve steepens brutally with die size, while D2W (5 bond steps per AMD V-Cache part) stays flat by only placing KGD. That's why AMD's D2W V-Cache was first to productize big-die stacking while W2W logic waited for a cheap top die (Graphcore's passive capacitor wafer).

“The ability to test and bond only known good die (KGD), instead of risking defects stacking and wasting good silicon, is critical and why die-on-wafer (D2W) is the first to be productized.”— Hybrid Bonding Process Flow - Advanced Packaging Part 5 (2024-02-09), SemiAnalysis

6. Intel's ~300-tool TCB bet looks economically irrational and is actually a moat: in high-margin silicon, yield beats tool amortization.

A TCB tool costs ~$1.25M and places 500-1,000 dies/hr vs ~$450k and 3,000-10,000/hr for flip-chip — yet Intel owns nearly 300 TCB tools and its $7B Malaysia facility will double that, using TCB even where flip chip would do. TCB kills CTE warpage, gap variation and tilt, enables 30µm-thin HBM dies and mixed 55µm/100µm pitches on one Sapphire Rapids package, and a decade of co-development means TSMC and Samsung can't instantly follow into Foveros-Omni-class assembly.

“Given Intel's heavy share in high power and high margin applications, the yield loss and reliability concerns far outweigh the miniscule, amortized cost of the tool per unit packaged.”— Advanced Packaging Part 3 – Intel's Curious Bet on Thermocompression Bonding (2022-01-19), SemiAnalysis

7. Chiplets aren't automatically cheaper — reticle utilization and Intel's Emerald Rapids re-aggregation both prove packaging intensity is a knob that turns both ways.

Two SemiAnalysis counterexamples to chiplet dogma. (1) Lithography is ~1/3 of wafer cost and scanners expose fixed 26x33mm fields: a 2-chiplet design that tiles the field badly needs 1.875x the scan steps, repricing the wafer $17,000→$21,364 and cutting the chiplet's saving from $136 to $26 — very likely more expensive than the 800mm2 monolithic die once packaging costs are counted. (2) Emerald Rapids went from four 394mm2 dies back to two 763mm2 dies: interface silicon fell 16.2%→5.8% of die area, EMIBs 10→3, core-area utilization 50.7%→62.7% — yet EMR still costs more per CPU than SPR (34 vs 37 CPUs/wafer) because big rectangles tile round wafers badly.

“If your yields are good, why waste area on redundant IO and chiplet interconnects when you can just use fewer, larger dies?”— Intel Emerald Rapids Backtracks on Chiplets (2023-05-03), SemiAnalysis

8. Graphcore Bow showed hybrid bonding is 'free' performance: +40% clocks from a capacitor wafer, with zero architecture, node or software change.

TSMC's first W2W SoIC product bonded a deep-trench-capacitor wafer under the same 7nm IPU: smoothing transient spikes lifted clocks from 1.325GHz to 1.85GHz (+40%) at +16% perf/W and equal cost. W2W TSVs run ~1/10th the pitch of chip-on-wafer — 10,000 connections where D2W fits 100. The same physics later let TSMC's CoWoS-R+ IPDs carry 6.4Gbps HBM3. Power delivery, not logic, is often the binding constraint 3D stacking relaxes first.

“In the area that chip-on-wafer hybrid bonding is able to offer 100 TSVs, the wafer-on-wafer technology can offer 10,000.”— Graphcore Announces World's First 3D Wafer On Wafer Hybrid Bond Processor (2022-03-03), SemiAnalysis

9. Packaging is the hyperscalers' commoditization weapon: Graviton3 shipped 55µm micro-bump chiplets, DDR5 and PCIe 5.0 before Intel or AMD.

Amazon's 7-die design (282mm2 compute + tiny DDR5/PCIe tiles) used ≤55µm bumps while every x86 CPU sat at ≥100µm, avoided AMD's ~100W IO-die power tax, dropped sockets for BGA to pack 3 CPUs per NIC per 1U — and SemiAnalysis exclusively identified the packaging vendor as 'a certain blue company' (Intel). AmpereOne extends the pattern: chiplets under a full carrier-wafer of structural silicon acting as CTE-matched heat spreader with direct-die cooling. System-level packaging choices, not core IPC, are what terrify merchant silicon.

“The size of the micro-bumps connecting each die are <=55um whereas every CPU from Intel and AMD is still at >=100um.”— Amazon Graviton 3 Uses Chiplets & Advanced Packaging To Commoditize High Performance CPUs (2021-12-02), SemiAnalysis

10. Tesla Dojo made the package the unit of scale: a wafer-scale InFO_SoW tile with 36TB/s off-tile bandwidth and vertical 15kW power delivery.

25 known-good D1 dies (645mm2, 400W each) are packaged into one fanout training tile — SemiAnalysis called the TSMC InFO_SoW packaging before Tesla's announcement. Each tile: 9 PFLOPS BF16, 36TB/s off-tile via a proprietary connector, ~10kW of silicon inside a ~15kW tile, with custom voltage regulators reflowed directly onto the fanout wafer so power enters vertically from below while heat exits above. It beat Cerebras on off-wafer bandwidth and previewed today's system-in-package direction for AI.

“This tile far surpasses anything from Nvidia, Graphcore, Cerebras, Groq, Tenstorrent, SambaNova, or any other AI training geared start up in per unit performance and scale up capabilities.”— Tesla Dojo - Unique Packaging and Chip Design (2021-08-20), SemiAnalysis

11. The 2.1D-2.5D lines are blurring: bridges, chip-last fanout and coreless ABF are eating the expensive silicon interposer from below.

EMIB and fanout-embedded bridges (MI250X, M1 Ultra) deliver most interposer benefits without full TSV-laden silicon; TSMC's CoWoS-R reaches 3x reticle with a 45x roadmap while CoWoS-S extends to just 4x. The supply chain logic favors chip-last flows that ship testable known-good substrates. Meanwhile ABF keeps densifying — 10µm L/S standard, 6µm Cisco coreless, 3µm Unimicron on panels, versus 2µm advanced fanout and 0.4-0.5µm Amkor SLIM/ASE NTI first layers. Nothing here is a stable monopoly except the substrate base itself.

12. The bonder market runs on a throughput-vs-accuracy lie: rated specs halve in the real world, and that gap is SemiAnalysis's 'very non-consensus view on BESI'.

TSMC's 3µm-pitch SoIC data: 98% bond yield below 0.5µm misalignment, resistance blowing out from 0.5-1µm, and 60% yield beyond 1µm. Besi's 8800 Ultra claims <200nm accuracy, but SemiAnalysis hears ~0.5µm with wide variance even at half rated throughput; a claimed 2,000 dies/hr drops under 1,000 at 1µm accuracy. Meanwhile Intel/CEA-LETI's capillary self-alignment hit 150nm mean misalignment with faster placement — a technology that could reset the D2W tool landscape entirely.

“Despite Besi's claims of 2,000 dies placed per hour, to reach even 1-micron accuracy, the throughput drops below 1,000 dies placed per hour.”— Packaging Developments From ECTC 2022 (2022-06-08), SemiAnalysis

13. TSV formation is the hidden gate on the AI supply chain — it bottlenecks both HBM and CoWoS, and avoiding TSVs is itself a product strategy.

Via-middle TSVs need deep reactive ion etch, insulation/barrier CVD, seed PVD, copper ECD fill and backside reveal — slow, tool-intensive steps. SemiAnalysis reports TSV formation bottlenecking HBM and CoWoS output, and notes customers switching from silicon interposers to CoWoS-R specifically to skip interposer TSV cost. Stacking economics compound: HBM dies thin to 30µm at 12-hi, forcing TCB today and pushing SK Hynix toward W2W hybrid bonding at 16-hi.

“We understand that TSV formation is a step that is bottlenecking HBM and CoWoS production.”— Hybrid Bonding Process Flow - Advanced Packaging Part 5 (2024-02-09), SemiAnalysis

14. The endgame beyond copper: optical interposers (Lightmatter Passage) promise 768Tbps per tile — but SemiAnalysis flags it may be vaporware.

Passage 3D-packages up to 48 customer ASICs on a wafer-scale photonic interposer (GF Fotonix 45CLO), stitching waveguides across reticles at 0.004dB loss per crossing, reconfiguring the whole fabric in <1ms with 2ns max chip-to-chip latency, and feeding 700W per tile through TSVs. It's ~40x the interconnect density of fiber-attach co-packaged optics. SemiAnalysis's caveats: the MZI fabric is one-in-one-out (much of the 768Tbps idles), and customers must trust an unproven partner with their most expensive silicon.

“This could just be vaporware, or it could be the future for high-end leading edge disaggregated server designs.”— Beyond Advanced Packaging: Lightmatter Passage Chiplets Co-Packaged On Optical Interposer (2022-08-22), SemiAnalysis

Article Deep-Dives

Hybrid Bonding Process Flow - Advanced Packaging Part 5 (2024-02-09)

The definitive process-flow primer. Walks TSV formation (via-middle DRIE + CVD/PVD/ECD + backside reveal, currently bottlenecking HBM/CoWoS), hybrid-bond layer fabrication (PECVD SiCN, damascene copper, ~5nm pad recess, multi-slurry CMP), probing/singulation particle management (laser/plasma over blade dicing — Disco), N2 plasma activation, and megasonic DI cleans. Frames the W2W vs D2W cost crossover around known good die, details collective D2W (AMD V-Cache = 5 bond steps) and Intel's QMC reconstituted W2W, and lists the full tool ecosystem (Besi, EVG, TEL, AMAT, ASMPT, SUSS, SET, Shibaura) with a teased 'very non-consensus view on BESI' and firm-level adoption modeling through 2030.

Packaging Developments From ECTC 2022 (2022-06-08)

The conference distillation that quantified the frontier: TSMC gen-4 SoIC at 3µm pitch (100k pads/mm2, 98% yield <0.5µm misalignment); Sony's 1µm-pitch hybrid bond with a contrarian protruding-copper CMP process delivering orders-of-magnitude better contact resistance; Intel/CEA-LETI water-droplet self-alignment (150nm mean misalignment, 98% bond yield) as a possible D2W disruptor; SK Hynix W2W hybrid bonding aimed at 16-hi HBM; Samsung's MCM/2.5D/3D power-area overhead study; AMD V-Cache's hidden 5th support die and its 17µm production pitch (vs 9µm marketing); plus ASE probing co-packaged optics and CoWoS-R+ carrying 6.4Gbps HBM3 via high-density IPDs.

Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets (2021-12-15)

The series manifesto. Chains the argument: real chip density lags transistor density (SRAM death, power, IO); flip-chip pitch stagnated for 20 years creating pad-limited designs (why Gelsinger's 'port automotive chips to Intel 16' fails); cost-per-transistor now rises (N7 $9.5k vs N5 $16k wafers); die sizes hit reticle limit; chiplets fix defect math (AMD's 3 tape-outs vs Intel's 5; a 2,000-step process at only ~99.98% good per step (~194 ppm) already sags to a cumulative D0=0.678, while true six-sigma at 3.4 DPMO would hold ~99.3%, so real semiconductor steps run at or beyond six-sigma quality) but not IO. Conclusion: 'we are in the midst of the semiconductor design renaissance which is being pushed forward by advanced packaging.'

Advanced Packaging Part 3 – Intel's Curious Bet on Thermocompression Bonding, ASM Pacific, Kulicke and Soffa, and Besi TCB Tool Landscape (2022-01-19)

Explains why TCB exists (batch reflow's CTE warpage, gap variation, tilt — AMD Fiji's field failures) and why Intel bought ~300 tools despite brutal economics ($1.25M/500-1,000 dph vs $450k/3,000-10,000 dph): in high-margin, high-power silicon, yield and reliability dwarf tool amortization, and one tool platform covers standard, 2.5D and 3D packages (SPR's mixed 55µm EMIB + 100µm pitches; Foveros Omni at 130/100/36µm is 'nigh on impossible' with standard flip chip). HBM's 30µm-thin 12-hi stacks make TCB mandatory for Samsung/SK Hynix/Micron. ASMPT, K&S and Besi each hold distinct niches; Intel's co-developed platforms are the largest orders.

The Future Of Packaging Gets Blurry – Fanouts, ABF, Organic Interposers, Embedded Bridges – Advanced Packaging Part 4 (2022-11-01)

Maps the 2.1D-2.5D middle ground where most volume will live. Four base classes (3D, 2.5D, fanout RDL, ABF build-up) blur via hybrid substrates: EMIB bridges in ABF cavities, MI250X's fanout-embedded bridges atop ABF, chip-first vs chip-last flows. Key supply-chain insight: the PC/DC industry runs on matching known-good substrates with known-good dies, so chip-last (testable substrate before die attach) is preferred if cost allows. The L/S race (ABF 10µm, coreless 6µm/3µm, EMIB 5→2µm, fanout 2µm, SLIM 0.4µm) means improving ABF keeps cannibalizing fanout — no packaging technology's moat is safe below the silicon interposer.

Die Size And Reticle Conundrum – Cost Model With Lithography Scanner Throughput (2022-06-19)

The free-article cost model that punctures chiplet dogma. Because a scanner exposes fixed 26x33mm fields (mask 104x132mm, 4x reduction) and lithography is ~1/3 of processed-wafer cost, a chiplet that tiles the field poorly forces 1.875x the scan steps; a margin-preserving foundry reprices the wafer from $17,000 to $21,364, shrinking the chiplet's silicon saving from $136 to just $26 per product ($541 vs $567); once packaging costs are added, the monolithic die is very likely cheaper. Caveats acknowledged (most real chiplet architectures improve utilization; High-NA halves the scan), but the discipline stands: die-size choice must be co-optimized with the reticle grid.

Reference: Value Chain

Front-end packaging foundries & IDMsTSMC (SoIC, CoWoS-S/R/L, InFO/InFO_SoW), Intel (Foveros/Omni, EMIB, TCB fleet), Samsung — Hybrid bonding's fab-grade cleanliness and toolset pulled leading-edge packaging inside the foundry. TSMC monetizes every rung (Apple InFO, Nvidia CoWoS, AMD SoIC, Tesla InFO_SoW); Intel counters with EMIB bridges, Foveros and a decade of co-developed TCB.

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OSATs (outsourced assembly & test)ASE/SPIL (FoCoS, NTI), Amkor (WLFO, SLIM), JCET, Fabrinet (optics) — Own bump, flip-chip, fanout and some TCB — but hybrid bonding needs ISO 1-3 cleanrooms plus CVD/etch/PVD/ECD/CMP experience they lack, so the highest-value new layer is structurally out of reach. ASE probing co-packaged optics threatens optics specialists like Fabrinet.

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Bonder & die-placement tool vendorsBesi (D2W HB, 8800 Ultra), ASMPT, Kulicke & Soffa (TCB niches), EV Group (dominant W2W, SmartView), SUSS Microtec, SET, Shibaura, Shinkawa, TEL (W2W win at TSMC) — The choke tools. EVG dominates W2W alignment (sub-50nm); Besi is the de-facto D2W hybrid bonder at TSMC but real accuracy runs ~0.5µm at half rated throughput — SemiAnalysis holds 'a very non-consensus view on BESI'. TCB demand splits across ASMPT/K&S/Besi niches, with Intel the largest buyer.

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Front-end equipment pulled into packagingApplied Materials, Tokyo Electron, Lam (dep/etch/CMP), Disco (dicing/grinding), ACM Research (megasonic clean), EVG/SUSS (activation) — Hybrid bonding is built from fab steps: PECVD SiCN, damascene copper, multi-pass CMP, plasma activation, DI-water megasonic cleans, laser/plasma dicing. Disco leads clean dicing ('their stock has more than tripled since we wrote about them'); every HB wafer means more front-end tool spend.

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Substrates & materialsAjinomoto (ABF film), Unimicron, Ibiden, Shinko, Samsung EM — ABF build-up substrate is the base of nearly every advanced package. Coreless ABF (Cisco 6µm L/S, 10 layers; Unimicron 3µm L/S on panels) is climbing into fanout's territory with the killer logistics advantage of shippable known-good substrates.

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Designers & vanguard adoptersAMD (3D V-Cache, MI250X/MI300X), Sony (CIS, 1µm pitch leader), Graphcore (first W2W logic), Apple, Nvidia, Amazon/Annapurna, Tesla, Ampere, SK Hynix/Samsung/Micron (HBM), Adeia/Xperi (DBI IP) — Adoption is led by whoever's economics break first: AMD stacked SRAM when it got cheaper than shrinking it; Sony stacks pixels; hyperscalers use packaging to ship DDR5/PCIe5 six months before x86 incumbents. Adeia licenses the underlying DBI hybrid-bonding IP.

Reference: Core Concepts

Advanced packaging (the <100µm definition) & the pitch ladder. SemiAnalysis defines 'advanced' as any packaging with bump pitch below 100µm (tool vendors calling all flip chip 'advanced' are ignored). The ladder vs standard flip chip (150-200µm): fanout at 90-60µm ≈8x IO density, 2.5D at 55-50µm ≈16x, 36µm micro-bump 3D ≈31x, 17µm hybrid-bonded TSVs ≈138x, Sony's 6.3µm CIS ≈567x (multipliers are all relative to standard flip chip (150-200µm), but the baseline is not uniform across rungs). Each rung is a step-function in interconnect density and energy-per-bit.

Pad-limited design (the IO wall). Transistors scaled 2x/2yr but IO data rates only 2x/4yr, and flip-chip bump pitch barely moved since the 1990s (AMD 200µm→130µm = only 2.35x more IO; Intel →100µm = 4x). Old designs ported to new nodes can't shrink because pads set the floor on die area — which is also why Gelsinger's 'move automotive chips to Intel 16' pitch fails on unit economics.

Chiplets & Known Good Die (KGD). Splitting big chips beats defect math (a 2,000-step process at only ~99.98% good per step (~194 ppm) already sags to a cumulative D0≈0.678 — true six-sigma (3.4 DPMO) would hold ~99.3%, so semiconductor steps run at or beyond six-sigma quality). AMD covers a huge market with 3 tape-outs vs Intel's 5. But chiplets add interface area, packaging yield risk, and power; the whole 3D-stacking economics question reduces to whether you can test and bond only known-good dies.

Hybrid bonding (bumpless Cu-Cu). Dielectric-to-dielectric plus direct copper-to-copper bonding with no solder: pads recessed ~5nm below a SiCN/SiO surface, pressed flush, then annealed. Scales below 10µm pitch with a roadmap into hundreds of nanometers; kills solder resistance so energy/bit plummets. Requires 0.5nm dielectric / 1nm copper surface roughness, multiple precision CMP passes, and via-middle TSVs to feed power and signal through the stack.

W2W vs D2W (wafer-on-wafer vs die-to-wafer). W2W bonds two whole wafers: sub-50nm alignment, cleaner, cheap, mature (Sony CIS, YMTC NAND, Graphcore Bow) — but both dies must be the same size and you stack defective dies onto good ones, so it loses on large low-yield logic. D2W picks and places known good dies: wins on big dies but is slower, dirtier (singulation particles), and less accurate. Collective D2W and self-assembly try to square the circle.

TCB (thermocompression bonding). One tool places each die, applies force + heat (+ vibration) to reflow solder in place — eliminating batch-oven CTE warpage, gap variation and tilt. It packages ultra-thin dies (HBM stacks; SK Hynix 12-hi HBM3 dies thinned to 30µm) and mixed pitches on one package. The catch: ~$1.25M per tool at 500-1,000 dies/hr vs ~$450k flip-chip placers at 3,000-10,000/hr.

2.5D: silicon interposers (CoWoS) vs bridges (EMIB). 2.5D stacks active silicon on a passive routing die at 55-50µm pitch — Nvidia GPUs + HBM on TSMC CoWoS-S is the volume case. Interposers are expensive (TSV-heavy), so the industry substitutes: EMIB embeds a small silicon bridge in the ABF substrate; CoWoS-R uses organic RDL (R+ adds high-density IPD capacitors to carry 6.4Gbps HBM3, with a roadmap to 45x reticle vs CoWoS-S extending to only 4x).

Fanout RDL & ABF build-up substrate. Fanout re-spreads a die's IO across a reconstituted wafer/panel (TSMC InFO in every Apple A/M chip; wafer-scale InFO_SoW in Tesla Dojo). ABF build-up substrate (Ajinomoto film) is the base of nearly everything — 'hybrid substrates'. The L/S race: ABF 10µm, Cisco coreless 6µm, Unimicron coreless 3µm, EMIB 5µm→2µm, advanced fanouts 2µm, Amkor SLIM 0.4µm — improving ABF keeps cannibalizing fanout from below.

Reticle limit & reticle utilization. A scanner exposes a 26mm x 33mm field (mask 104x132mm at 4x reduction); Nvidia/Intel datacenter dies have sat near this limit for 5+ years. Less obvious: lithography is ~1/3 of processed-wafer cost, and a chiplet that tiles the field badly forces more scan passes — SemiAnalysis's example needs 1.875x the steps, repricing the wafer from $17,000 to $21,364, shrinking the chiplet's silicon saving to just $26 — and very likely making the 'cheaper' chiplet dearer than monolithic once packaging costs are added.

Open Questions

When does D2W hybrid bonding get cheap enough to spread beyond AMD — into mobile, client PCs and AI accelerators? SemiAnalysis's adoption model runs to 2030, but through early 2024 the answer was 'one customer'.
Can pick-and-place bonders economically reach sub-200nm accuracy, or do collective flows and capillary self-assembly (Intel/CEA-LETI's 150nm) reset the tool landscape — and with it Besi's presumed moat?
Do OSATs ever climb into hybrid bonding, or is leading-edge packaging permanently annexed by TSMC and Intel, leaving ASE/Amkor the commoditizing layers?
In HBM, when does hybrid bonding displace TCB? 16-hi stacks with 30µm dies strain solder physics, yet TCB keeps being extended — the crossover timing moves billions in tool orders.
Where is the true chiplet/monolithic frontier once reticle utilization, interface overhead and packaging yield are all priced — will more designs 'do an Emerald Rapids' and re-aggregate as nodes mature?