AI Supply Chain Research · Sector 03

Memory & HBM

DRAM stopped scaling a decade ago; AI turned that broken physics into the highest-margin product memory has ever sold. HBM is where the money, the yield pain, and the geopolitics all collide.  ·  ← back to the series  ·  Background: Primer §00, §01, §02, §03, §04, §05, §06, §09, §10

At a glance
Winners
SK HynixMicronTSMCHanmi (TC bonders) / EVG / TELCXMT (speculative)
Bottlenecks
CoWoS interposer capacity — the real gate on AI accelerator supply; 1,000+ wires can't be routed on PCB, so silicon interposers are mandatory.HBM front-end TSV/PDN yield and 12-hi+ stacking losses — the binding constraint on effective HBM bit supply (why Rubin Ultra uses 12-hi not 16-hi HBM4E).TC-bonder supply — a single-vendor dependency (Hanmi) that nearly halted Hynix HBM in April 2025.GPU 'shoreline' area — HBM limited to 2 SOC edges, capping how many stacks fit per package.Fab construction lead times — too long to react, which is exactly why the shortage persists to ~2028.
Risks
Cyclicality: memory is the most cyclical semi sub-industry; ASP-driven earnings (esp. CXMT) reverse violently when the cycle turns.Samsung wildcard: perennially over-promises aggressive tech (hybrid bonding), then fails execution — but is genuinely closing the HBM4 gap. Its bad HBM yield ironically tightens total DRAM supply.China oversupply overhang: overplayed for the next ~2 years per SemiAnalysis, but CXMT/Huawei custom non-JEDEC HBM + government self-sufficiency push are a longer-term structural threat.Interface/IP disruption: modern base-die PHYs (Eliyan UMI/NuLink, UCIe) could reshuffle where value accrues and even reduce HBM capacity needs — 'someone is going to win big in the IP wars.'Export-control leakage: reclaimed/smuggled HBM and reexport loopholes blunt controls and quietly feed Chinese accelerators.
Catalysts
CXMT STAR Market IPO — likely China's largest-ever semiconductor listing; a valuation and disclosure event for the whole China memory complex.HBM4 ramp (2026-27) — base-die-on-foundry-node transition; Samsung's competitive re-entry vs Hynix; custom base dies for OpenAI/Nvidia/AMD/Amazon.DRAM price doubling in 2026 — the 'once-in-four-decades shortage' spanning HBM/DDR5/DDR4/DDR3, potentially exceeding forecasts by year-end.Server DRAM + HBM crossing >50% of DRAM demand by end-2027 — mix shift that widens leader ASP over CXMT.Rubin Ultra (1TB HBM4E/GPU) and Amazon direct-HBM procurement — the next leg of per-chip capacity and a new buying model.

Overview

Memory is the quiet chokepoint of the AI buildout. SemiAnalysis's throughline across this bucket: DRAM bit-density scaling collapsed from 2x-every-18-months to 2x-per-decade, so the industry can no longer cushion price with cost-down, leaving a consolidated 3-player oligopoly (SK Hynix, Samsung, Micron) plus rising CXMT that swings violently on supply. HBM is the release valve — vertically stacked DRAM with a 1,024-bit (soon 2,048-bit) bus, glued to the GPU by CoWoS, now ~60%+ of Blackwell's manufacturing cost and the single largest BOM increase generation-over-generation. It is also the hardest DRAM ever made: front-end TSV yield and 8-to-16-high stacking losses run far below normal DRAM, which is exactly why it is margin-accretive. The frontier is HBM4, which splits the base die onto a foundry logic node (TSMC N12 for Hynix, SF4 for Samsung, internal for Micron) and opens the door to custom base dies for OpenAI/Nvidia/AMD/Amazon. Beneath HBM sits the slower war over how to keep DRAM alive at all — 4F2 vertical-channel cells, hybrid-bonded cell-on-peri, and eventually 3D DRAM (~2030-2035) — plus a once-in-four-decades shortage that has DRAM pricing set to double again in 2026. NAND runs a parallel story: layer-count racing (332L), 5-bits-per-cell, and China's YMTC/CXMT breaking the cartel from below.

Positioning: Who Wins and Why

SK Hynix — Clear HBM leader on MR-MUF packaging and reliability; primary beneficiary of every HBM content increase in Nvidia's roadmap; highest gross margin of the majors (60.4% FY25) thanks to its HBM mix. TSMC partners on its HBM4 N12 base die.

Micron — Leapfrogged into HBM on TSV/power-delivery focus (claims ~30% lower power), matches Hynix NAND density with fewer/cheaper decks, and rides the broad DRAM shortage. Uses a lower-cost internal CMOS HBM4 base die. Also a FeRAM leader.

TSMC — Owns the CoWoS interposer that is the real AI packaging bottleneck AND the foundry logic node (N12) for HBM4 base dies — double exposure to HBM's growth without making DRAM. Also fabs custom base dies for OpenAI/Nvidia/AMD.

Hanmi (TC bonders) / EVG / TEL — Hanmi held a near-monopoly on HBM thermocompression bonders (100% at Hynix until recently). EVG/TEL gain from wafer-bonding tools needed for VCT/4F2 and hybrid-bonded cell-on-peri DRAM. Lam dominates cryo high-aspect-ratio NAND etch.

CXMT (speculative) — Rising #4 DRAM maker, ~13%->17% wafer share, riding the same pricing supercycle to a first-ever profit and a landmark IPO — but it's an ASP play, not a technology one, and still 30%+ behind on cost/bit.

Key Data

MetricValueNote
DRAM density scaling~2x in the last decade (vs 2x every 18 months in the golden age = ~100x/decade)The single fact behind memory's structural scarcity and cyclicality.
HBM share of AI GPU manufacturing costH100 ~50%+ -> Blackwell ~60%+Biggest absolute & relative BOM increase Ampere->Blackwell Ultra; a wealth transfer to SK Hynix.
HBM price premium vs DDR53x+ per GBCustomers pay it because no other DRAM makes a competitive accelerator.
HBM stack-yield compounding99%/layer -> 92% at 8-hi, ~89% at 12-hiIllustrative; real yield degrades faster as non-critical defects accumulate.
Samsung HBM4 (ISSCC 2026)36GB 12-hi, 3.3 TB/s, 2,048 IO, 13 Gb/s/pin, VDDQ 0.75V~1.6x the JEDEC HBM4 spec (8 Gb/s, ~2 TB/s); 1c DRAM + SF4 base die.
HBM4 base-die foundry splitHynix = TSMC N12; Samsung = SF4; Micron = internal CMOSSF4 is the most expensive; Hynix/Micron chose lower-cost paths.
Samsung 1c HBM4 front-end yield (2025)~50% (improving)Samsung skipped 1b, jumping 1a->1c; a margin risk on HBM4.
DRAM energy split (interface vs cell)DDR5 >99% interface; HBM ~95% interface / 5% cellThe waste that motivates compute-in-memory and modern base-die PHYs.
Bank potential vs delivered bandwidth~4 TB/s/chip potential; HBM die delivers only ~1/16 (256-bit bus)UCIe PHY could reach ~11 Tbps/mm (~12x HBM3E), energy/bit 2pJ->0.25pJ.
CXMT FY25 financialsRevenue ~$8.6B (+156% YoY), first-ever net profit ~1.88B yuan (~$275M) — turnaround from 2024 net loss ~7.14B yuan (~$1B), GM 37.8%1Q26: $7.3B rev (~700% YoY), ~70% op-margin — ASP-driven, not share.
CXMT vs incumbents DRAM revenue (CY25)CXMT ~$8.6B vs Samsung ~$72.3B, SK Hynix ~$52.1B, Micron ~$37.2BClear #4 globally, but still an order of magnitude behind the leaders.
CXMT DDR5 cost-per-bit gap>30% higher than the big-3; ASP only 5-10% below leadersMargin is pricing, not product competitiveness this cycle.
CXMT HBM3 8-hi modeled yield~35% front-end x ~70% back-end ~= 25% overallStruggling on 8-hi, greater challenges at 12-hi; likely skips HBM3 for HBM3E.
DRAM wafer capacity (end-2026E)Samsung ~720k, SK Hynix ~595k, Micron ~385k, CXMT ~350k wspmCXMT closing on #3 Micron by wafers; global DRAM share ~13%->17%.
SanDisk/Kioxia BiCS10 NAND332 layers, 3 decks, 37.6 Gb/mm2 QLC (world's densest)vs SK Hynix 321L V9 at 28.8 Gb/mm2 QLC — 30% behind.
SK Hynix V9 321L density gain+44% memory/wafer over 238L V8; +30% process steps, +20% etch stepsLayer count up ~35% — outrunning process-step growth, so still cost-down.
Emerging memory densityMRAM 0.49 Gb/mm2 > Micron D1b DRAM 0.435; ships in MB not GBFeRAM matched D1b density at IEDM 2023 but too costly; not DRAM replacements.
Marvell Custom HBM1,024 channels @ 32 Gb/s ~= 4.1 TB/s per stack; ~60% smaller host-ASIC HBM-PHY footprintCustom base die + organic RDL (ECTC 2026, SemiAnalysis).
Samsung HBM4E interposer/thermalHBM4E needs ~2x the interposer layers of HBM3E; hybrid-copper-bond (HCB) cuts in-stack thermal resistance ~12%Packaging/thermal cost of HBM4E (ECTC 2026, SemiAnalysis).

Key Theses

1. DRAM's scaling death is the whole story: density went from 2x every 18 months to 2x per decade.
Moore's Law for DRAM died a decade ago with zero fanfare. Because DRAM is commoditized and has almost no cost-down to cushion price, it can't behave like logic — the only way to add supply is to build new fabs, so wild price swings and huge capex leave a top-3 oligopoly owning >95% of the market. This is the structural reason memory is so cyclical and why AI-driven scarcity is so violent.
“The world increasingly questions the death of Moore's Law, but the tragedy is that it already died over a decade ago with 0 fanfare or headlines.”— The Memory Wall: Past, Present, and Future of DRAM (2024-09-03), SemiAnalysis
2. HBM is now the majority of an AI GPU's manufacturing cost — ~60%+ on Blackwell.
For the H100, 50%+ of manufacturing cost is HBM; on Blackwell it grows past 60%. Nvidia's roadmap scales HBM from the A100's 80GB HBM2E to 1,024GB HBM4E on Rubin Ultra, and from Ampere to Blackwell Ultra the single biggest absolute and relative BOM increase is HBM — a direct wealth transfer to memory vendors, primarily SK Hynix. HBM3E costs 3x+ per GB versus DDR5 and customers pay it because no other DRAM makes a competitive accelerator.
“For the H100, ~50%+ of the cost of manufacturing is attributed to HBM and with Blackwell, this grows to ~60%+.”— The Memory Wall: Past, Present, and Future of DRAM (2024-09-03), SemiAnalysis
3. The memory market has entered a 'once-in-four-decades shortage'; DRAM pricing is set to double again in 2026.
SemiAnalysis first flagged AI's insatiable reasoning/agentic memory demand in late 2024. The shortage now spans not just HBM but DDR5, DDR4 and even DDR3, with the firm 'even more confident' pricing could exceed expectations by year-end. Even factoring in CXMT and peer wafer adds at high-90s% utilization, they model DRAM undersupplied by a high-single-digit % in 2026, widening to low-to-mid-teens bit undersupply in 2027, potentially through 2028 — because fab construction timelines are simply too long to react.
“we described the memory market as entering a 'once-in-four-decades shortage,' we believe DRAM pricing remains on track to double again this year driven by sustained supply-demand imbalance”— China's CXMT Is Set to Challenge DRAM Incumbents (2026-06-23), SemiAnalysis
4. HBM's yield pain — front-end TSV/PDN, not just stacking — is precisely why it's margin-accretive.
All makers run absolute HBM yields well below their conventional DRAM, so it's a game of relative yields and end economics. Yield compounds with layers (99% per-layer -> 92% at 8-hi, ~89% at 12-hi). The bigger problem is front-end: delivering power up the stack via power-TSVs. Hynix's all-around power TSVs cut IR drop up to 75% for VPP; Micron's TSV/PDN focus lets it claim 30% lower power. Because pricing more than covers yield loss, HBM is the most valuable, highest-margin product the memory industry has ever had.
“As data from hyperscalers have shown, HBM failures are the number one cause of GPU failures, which happen more frequently than other chips in the data center.”— Scaling the Memory Wall: The Rise and Roadmap of HBM (2025-08-12), SemiAnalysis
5. HBM4 is a tectonic shift: the base die moves to a foundry logic node, and Samsung has clawed back into contention.
HBM4 splits process nodes — DRAM node for core dies, advanced logic node for the base die. At ISSCC 2026 Samsung showed a 36GB 12-hi HBM4 at 3.3 TB/s with 2,048 IO on 1c DRAM + an SF4 logic base, hitting 13 Gb/s/pin (~1.6x the JEDEC HBM4 baseline of 8 Gb/s) while dropping VDDQ 32% from 1.1V to 0.75V. Hynix uses cheaper TSMC N12, Micron an internal CMOS base — both lower-cost than Samsung's SF4. Samsung's 1c yields ran ~50% in 2025, a margin risk, but its technology gap to Hynix has meaningfully closed.
“Samsung's paper claimed that the ABB and the 4x higher TSV count allow their HBM4 to achieve operating speeds up to 13 Gb/s per pin.”— ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6... (2026-04-15), SemiAnalysis
6. The DRAM interface is grotesquely wasteful — 95-99% of read/write energy is spent in the interface, not the cells.
DRAM lacks an autonomous general-purpose memory controller and leans on the host for scheduling — though the die itself carries substantial command/address decode, timing, refresh, training and on-die RAS logic; commands funnel through one ancient half-duplex interface. DDR5 DIMMs burn >99% of read/write energy in the host controller/interface; even HBM is ~95% interface, 5% cell. Worse, an HBM die's 256-bit bus taps only ~1/16 of the banks' true ~4 TB/s potential. This is the opening for compute-in-memory and modernized base-die PHYs (UCIe: ~11 Tbps/mm, ~12x HBM3E; energy/bit from 2pJ to 0.25pJ). 'Someone is going to win big in the IP wars.'
“DDR5 DIMMs, the most common on servers, expend more than 99% of read or write energy in the host controller and interface.”— The Memory Wall: Past, Present, and Future of DRAM (2024-09-03), SemiAnalysis
7. CXMT's explosive earnings are a cycle story, not a competitiveness story — its cost-per-bit is still 30%+ worse.
CXMT FY25 revenue rose 156% to ~$8.6B, first-ever net profit ~1.88B yuan (~$275M) — a turnaround from the 2024 net loss of ~7.14B yuan (~$1B); 1Q26 revenue $7.3B (~700% YoY) at ~70% op-margin. But sequentially (QoQ) its 1Q26 bit shipments grew only ~11% while ASP rose ~57% — so the ~700% YoY revenue jump is price-led, not volume-led; the earnings are ASP, not share. On DDR5, CXMT's cost-per-bit is still >30% higher than the big-3; ~38% gross margin is pricing, not product. The old 'Chinese memory will flood and crush pricing' fear is, this cycle, inaccurate — CXMT ASP sits only 5-10% below the leaders.
“such significant upside to CXMT's earnings is clearly driven more by the cycle itself than company's technology or market positioning.”— China's CXMT Is Set to Challenge DRAM Incumbents (2026-06-23), SemiAnalysis
8. CXMT is deliberately choosing commodity DRAM over HBM — because commodity DRAM currently earns more.
~99% of CXMT's 2025 revenue is DDR/LPDDR; only ~5 of ~265 kwspm went to HBM in 2025. Its HBM3 8-hi is modeled at ~35% front-end and ~70% back-end yield = ~25% overall, so HBM would be low-margin and consume scarce DRAM wafers that yield 3x more bits as commodity. So prioritizing commodity is rational — but Beijing's self-sufficiency push conflicts with that, forcing CXMT's HBM wafer capacity up to a modeled 55/100 kwspm in 2027/2028 (1%->12% of global HBM wafers). The IPO prospectus discloses NO dedicated HBM project.
“The commodity DRAM currently offers materially higher margins than CXMT's HBM products, while also delivering more than 3x the bits per wafer on a like-for-like basis.”— China's CXMT Is Set to Challenge DRAM Incumbents (2026-06-23), SemiAnalysis
9. Hybrid bonding for HBM keeps slipping; JEDEC chose to just make the stack taller (720um->775um) instead.
Hybrid bonding is bump-less, freeing room for more layers, but D2W HB yield for even 2 layers is hard/expensive — imagine 16. HBM3/3E hit the 12-hi limit inside the 720um JEDEC cube; the two ways up are bump-less or taller. In a blow to HB, JEDEC relaxed height to 775um. HB for HBM keeps sliding from HBM4 to '4E'; Hynix and Micron have gone quiet, only Samsung loudly promotes it — 'typical for Samsung which often promotes the most aggressive technology... only to expectedly fail on execution.'
“All initial HBM4 will not use hybrid bonding, and we expect that to remain true for much longer than most would hope.”— The Memory Wall: Past, Present, and Future of DRAM (2024-09-03), SemiAnalysis
10. 'Memory-Parkinson': every HBM capacity bump is instantly eaten by bigger models, so memory is always the next bottleneck.
In inference, weights live permanently in HBM alongside a KVCache that grows every token; decode repeatedly reads both, so most LLM inference is bandwidth-bound. As reasoning models 'think' for tens of minutes (Deep Research) with 100k+ token contexts, capacity pressure explodes and serving at low batch sizes hurts economics. Each capacity jump (80GB/3.35TB/s H100 -> 192GB/8TB/s GB200) just resets the baseline for 'reasonable' model size. RL/inference is now the main driver of progress, permanently structural for memory demand.
“as AI chips get more HBM, developers immediately build larger models to fill it, so memory is always the next bottleneck.”— Scaling the Memory Wall: The Rise and Roadmap of HBM (2025-08-12), SemiAnalysis
11. SRAM scaling is dead too — MediaTek's logic-based xBIT is a workaround, not a cure.
From N5 to N2, logic area fell 40% but 6T-HC SRAM bitcells shrank only 2% (8T-HC 18%); N3E's HD bitcell even regressed to N5 density. SRAM is ~120 F2 — 20x less dense than DRAM's 6F2. MediaTek's 10-transistor xBIT (balanced 4/6 NMOS/PMOS) gets 22-63% higher density and 30%+ lower power vs a standard 8T cell, using pure logic rules. It shows how hard on-die cache scaling has become — reinforcing the case for offloading capacity to HBM/LPDDR tiers instead.
“Despite logic area decreasing by 40% from N5 to N2, 8-transistor high-current SRAM bitcells have only decreased in area by 18%. 6-transistor high-current (6T-HC) bitcells are even worse, only decreasing by 2%.”— ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6... (2026-04-15), SemiAnalysis
12. NAND is a layer-count and bits-per-cell race — and SK Hynix is quietly losing the density war.
SanDisk/Kioxia's BiCS10 (332L, 3 decks) is the world's densest at 37.6 Gb/mm2 QLC, dethroning Hynix's 321L V9 (28.8 Gb/mm2 QLC / 21 Gb/mm2 TLC — 30% behind). Micron matches Hynix's density with only 2 decks (lower cost). Since AI has choked cleanroom space, makers can only upgrade existing lines, so denser processes = more supply per constrained wafer. SK Hynix's exotic answers (Mo wordlines, 5-bits-per-cell multi-site cell) are R&D-stage, not yet cost-effective.
“SanDisk and Kioxia demonstrated their BiCS10 NAND, with 332 layers and 3 decks. This is the highest reported NAND bit density, at 37.6 Gb/mm2, dethroning the previous champion, SK Hynix's 321L V9.”— ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6... (2026-04-15), SemiAnalysis
13. The real AI-memory bottleneck isn't the DRAM cell — it's CoWoS advanced packaging co-locating HBM and logic.
HBM3E needs 1,000+ wires between XPU and memory — undoable on PCB/substrate, so a silicon interposer (CoWoS-S) is mandatory. That capacity, not GPU dies, gated 2023-24 supply. The flow (TSV interposer -> chip-on-wafer flip-chip reflow -> wafer-on-substrate) spans ~28 upstream vendors; SemiAnalysis argues the market misprices which of them actually win. Because HBM is limited to the SOC's two shoreline edges (the other two are for off-package I/O), 'shoreline area' becomes a first-order design constraint.
“the primary limiting factor is the CoWoS advanced packaging to put the 5nm ASICs and HBM together.”— AI Expansion - Supply Chain Analysis For CoWoS And HBM (2023-07-26), SemiAnalysis
14. China's HBM will come via custom, non-JEDEC designs — and via reclaimed HBM smuggled out of GPU packages.
US export controls (Dec 2024) ban raw HBM stacks into China, but chips containing HBM can ship if under FLOPS limits — so banned HBM is reexported (via CoAsia/Faraday/SPIL) and desoldered/reclaimed from GPU packages. Huawei runs its own HBM affiliates (XMC fab + SJSemi packaging, both entity-listed). Critically, Huawei and CXMT will use custom HBM that bypasses slow JEDEC standards/PHYs, letting them close the bandwidth gap without matching the incumbents' interface roadmap.
“Huawei and CXMT will have custom HBM that is not based on the slow JEDEC standards and phys, so it will be able to close the bandwidth disadvantage.”— China's CXMT Is Set to Challenge DRAM Incumbents (2026-06-23), SemiAnalysis

Article Deep-Dives

Scaling the Memory Wall: The Rise and Roadmap of HBM (2025-08-12)
The definitive HBM primer and roadmap. Explains why HBM's wide bus + vertical stack demands an interposer (1,000+ wires), why front-end TSV/PDN yield (not just stacking) is the real problem, and why it's still margin-accretive. Details the SK Hynix-Hanmi TC-bonder monopoly fight that nearly halted HBM shipments in April 2025, the shoreline-area constraint, KVCache offload to LPDDR/NVMe tiers, and the 'memory-Parkinson' dynamic. Covers HBM4's custom base die, JEDEC's 720->775um height relaxation (a blow to hybrid bonding), and China's CXMT/Huawei domestic HBM push. Nvidia still commands the lion's share of HBM demand through 2027 (Rubin Ultra = 1TB/GPU).
The Memory Wall: Past, Present, and Future of DRAM (2024-09-03)
The bucket's intellectual backbone. Traces DRAM from the 1T1C cell + sense-amp inventions to today's stagnation (capacitors at ~100:1 aspect ratio, ~40,000 electrons/cell, sense-amp sensing limits). Lays out the full scaling menu: near-term 4F2 + vertical-channel transistors (~50% theoretical density gain), medium-term compute-in-memory (banks have ~4 TB/s potential but interfaces tap ~1/16), custom HBM4 base dies, emerging FeRAM/MRAM (denser than DRAM but ship in MB), and long-term 3D DRAM. Key insight: DRAM's 'dumb' half-duplex interface wastes 95-99% of read/write energy — the opening for a new PHY/IP war.
China's CXMT Is Set to Challenge DRAM Incumbents (2026-06-23)
The definitive CXMT deep dive ahead of its STAR Market IPO (likely China's largest semiconductor listing). Traces its origins: licensed ~7,000 Qimonda patents + 2.8TB of docs + poached Qimonda/Korean/Taiwanese/US talent (Kuesters, Ping) + patient Hefei state-VC that absorbed ~RMB36.65B of accumulated losses over a decade. Verdict: explosive 1Q26 earnings ($7.3B, ~70% op-margin) are cycle/ASP-driven, not competitiveness — DDR5 cost/bit still >30% worse, HBM barely 5 kwspm and ~25% yield. Debunks the 'China floods and crushes pricing' fear this cycle. Flags the IPO's consolidation accounting (74% minority interest) and lack of any disclosed HBM project.
ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6, TSMC Active LSI, Logic-Based SRAM, UCIe-S and More (2026-04-15)
The frontier scorecard. Samsung's HBM4 (36GB 12-hi, 3.3 TB/s, 13 Gb/s/pin, VDDQ 0.75V) confirms it has closed the gap on Hynix technically, though it still trails on reliability and 1c yield (~50%). Samsung & SK Hynix LPDDR6 (up to 14.4 Gb/s, dual sub-channel efficiency mode), SK Hynix 1c GDDR7 (48 Gb/s). Samsung 4F2 COP DRAM cuts core-circuit area 17.0%->2.7% via hybrid-bonded cell-on-peri (but suffers floating-body leakage). SanDisk/Kioxia BiCS10 (332L) takes NAND density crown. MediaTek's logic-based xBIT SRAM cell and TSMC N16 MRAM round out the 'scaling is dead, find workarounds' theme.
Interconnects Beyond Copper, 1,000 CFETs, SK Hynix Next-Gen NAND, 2D Materials, and More (IEDM) (2026-01-13)
The NAND scaling deep dive amid the supercycle. With no cleanroom space for new capacity, makers can only densify existing lines: SK Hynix's 321L V9 packs +44% memory/wafer over V8 by adding a 3rd deck (etch limit ~120 layers/deck). But its 21 Gb/mm2 TLC trails Micron (2 decks, cheaper) and is dwarfed by BiCS10 (29 Gb/mm2 TLC, 37+ QLC). Samsung switches NAND wordlines W->Mo for performance and skips 3xx layers (286L->43xL). The standout: SK Hynix's multi-site cell splitting the channel to enable 5-bits-per-cell — R&D only, not yet cost-effective.

Reference: Value Chain

DRAM/HBM makers (the oligopoly)SK Hynix, Samsung, Micron, CXMT (China) — Top 3 own >95% of DRAM; SK Hynix leads HBM on MR-MUF and reliability, Micron leapfrogged on TSV power delivery, Samsung struggles on yield but its bad HBM yield ironically tightens total DRAM supply. CXMT is the rising #4.
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Foundry base-die & interposerTSMC (N12 base die, CoWoS interposer), Samsung Foundry (SF4), UMC — HBM4 shifts the base die onto foundry logic nodes; TSMC is Hynix's announced partner. TSMC also fabricates the silicon interposer that co-packages HBM+logic in CoWoS — the actual AI packaging bottleneck.
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Back-end bonding & packaging toolsHanmi, Hanwha, ASMPT, Besi (TC bonders); Namics (MUF material) — TC bonders need sub-micron alignment across ~40um TSV pitch. Hanmi held a near-monopoly at SK Hynix (100% until Hynix ordered Hanwha tools at a higher price) — the dispute nearly halted Hynix HBM shipments in 2025.
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Front-end WFE (TSV/etch/deposition)Applied Materials, Lam Research, TEL, EVG (wafer bonding), Camtek/Onto (bump inspection) — TSV etch/plate + double-side bumping convert DDR wafers to HBM. Lam dominates the high-aspect-ratio (cryo) channel etch central to 3D NAND; TEL is encroaching. EVG/TEL gain from wafer-bonding for VCT/4F2 DRAM.
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NAND makersSanDisk/Kioxia, Samsung, SK Hynix, Micron, YMTC (China) — Layer-count race (SanDisk/Kioxia BiCS10 = 332L, world's densest at 37.6 Gb/mm2 QLC), Mo wordlines, 5-bits-per-cell R&D. YMTC broke in as first Chinese tech-competitive semiconductor (128L, then 232L+).
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Custom-HBM / interface IP & buyersEliyan (UMI/NuLink), Nvidia, OpenAI, AMD, Amazon (direct HBM buyer) — Hyperscalers/labs now spec custom base dies and buy HBM directly (Amazon) to cut cost. Interface startups (Eliyan, funded by Micron/Intel) push UCIe-class PHYs (~11 Tbps/mm, ~12x HBM3E) to let HBM sit farther from the ASIC.

Reference: Core Concepts

HBM (High Bandwidth Memory). A 3DIC stack of 8-16 DRAM dies on a logic base die, connected by 1,000+ TSV wires and a 1,024-bit bus (2,048-bit in HBM4). It trades a warranted 3x+ price premium over DDR5 for the bandwidth AI accelerators need; every leading GenAI training/inference chip uses it. Needs fine-pitch on-package routing near the accelerator; implementations include full silicon interposers (CoWoS), RDL variants, and embedded silicon bridges (EMIB).

The Memory Wall. DRAM density doubled every 18 months in its golden age (100x/decade); in the last decade it managed only ~2x. Compute keeps racing ahead while memory bandwidth crawls, so most LLM inference is memory-bandwidth-bound, not compute-bound — the GPU waits on HBM. 'Moore's Law is dead for DRAM' — and it died a decade ago with zero fanfare.

TSV & stacking yield. Through-Silicon Vias carry power/signal up the HBM stack; forming them (etch/plate/grind/bond) is the incremental step that converts DDR wafers to HBM, so HBM capacity is quoted in 'TSV capacity.' Yield compounds badly: at 99% per-layer bond yield an 8-hi stack yields 92%, a 12-hi only ~89%. Front-end (power-TSV/PDN) is the bigger yield problem, not the stack.

MR-MUF vs TC-NCF (packaging). SK Hynix's Mass Reflow-Molded Underfill uses a single over-mold and batch reflow (co-developed with Namics), giving higher productivity and better thermal dissipation than the Non-Conductive Film (TC-NCF) that Micron and Samsung use, where each layer needs a full thermocompression bond. This is a core reason Hynix leads HBM3E while Samsung struggles to yield.

HBM4 custom base die. HBM4's big architectural break: the core DRAM dies stay on a DRAM node, but the base die moves to a foundry logic node (FinFET), enabling higher speed, lower voltage, and customer-specific customization. Hynix uses TSMC N12; Samsung uses its own SF4; Micron uses an internal CMOS base. Opens memory-controller offload, repeater PHYs and per-customer base dies for OpenAI/Nvidia/AMD.

4F2 & Vertical Channel Transistor (VCT). The next DRAM cell shrink: 4F2 is the theoretical minimum single-bit cell (a 6F2->4F2 move reduces ideal cell area ~33% and raises ideal density ~50% before periphery/layout overhead) and requires a vertical-channel transistor stacked under the capacitor. Paired with hybrid-bonded cell-on-peripheral (COP/PUC), core circuitry hides under the array — Samsung cut core-circuit area from 17.0% to 2.7%. China's CXMT already ships a 4F2 18nm DRAM.

3D DRAM. The endgame when vertical capacitors can't shrink further: lay capacitors horizontally and stack many atop each other (like 3D NAND did). Micron calls timing 'the quintessential question'; IMEC/Micron roadmaps put insertion ~2030-2035. Tellingly, none of the big-3 present serious 3D DRAM papers — it's the race that will reshuffle market share.

LPDDR as 2nd-tier memory / KVCache offload. HBM is scarce, so systems tier memory: hot KV/weights in HBM, warm data in cheaper LPDDR/DDR, cold in NVMe (Nvidia's Dynamo KVCache Manager). LPDDR uses ~10x less energy/bit than DDR5 DIMMs (Grace ships 480GB usable). Crucially SemiAnalysis argues these don't cannibalize HBM — like L1/L2 cache vs DRAM, they're complements, not substitutes.

Emerging memory (FeRAM/MRAM). Non-volatile alternatives researched for decades but none has 'emerged' to high volume. Micron's FeRAM matched D1b DRAM density at IEDM 2023 but is too costly (exotic materials). MRAM (magnetic tunnel junction) reached 0.49 Gb/mm2 — denser than D1b DRAM — but ships in MB, not GB. TSMC's N16 STT-MRAM is real, but only as embedded NVM for automotive/edge, not a DRAM replacement.

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Sources (SemiAnalysis)

Independence & sourcing. This is independent analysis by Yicheng Yang, distilled from publicly accessible SemiAnalysis articles (free posts and free previews; no paywall circumvention) and verified against the underlying text. It is not affiliated with, endorsed by, or a substitute for SemiAnalysis — subscribe there for the full research. All referenced claims are sourced and linked per SemiAnalysis's attribution terms. No SemiAnalysis images are reproduced. Nothing here is investment advice.