AI Supply Chain Research · Sector 02

Foundry & Advanced Process

One square mile in southern Taiwan makes the transistors the entire AI economy runs on — and the whole industry is now fighting over N3 wafers, backside power, and whether anyone can ever build a second TSMC.  ·  ← back to the series  ·  Background: Primer §00, §01, §02, §05, §06, §09, §10

At a glance
Winners
TSMC (TSM)ASMLDeposition/etch/metrology WFE (Applied Materials, Lam, KLA, TEL)Intel Foundry (INTC) — high-risk turnaroundGlobalFoundries (GFS) — specialty niche
Bottlenecks
TSMC N3 front-end wafer capacity — the single biggest constraint on AI accelerator output; utilization >100% in 2H26, gated by cleanroom construction lead time.EUV lithography tools — ASML production isn't scaling measurably; a hard ceiling on how fast any foundry can add leading-edge capacity.HBM and advanced packaging (CoWoS/SoIC) — the co-requisite for AI accelerators; HBM eats ~3x DRAM wafers per bit, packaging capacity moves in lockstep with N3.Taiwan engineering talent — only so many Taiwanese engineers exist to spin up foreign fabs, structurally capping the speed of onshoring.
Risks
Taiwan concentration / cross-strait conflict — ~3% of US GDP and 8 of the 10 largest firms depend on one square mile; the tail risk that dwarfs all others.AI capex air-pocket — the N3 shortage is built on multi-year AI compute commitments; a demand reset would leave TSMC with the industry's most expensive idle capacity (see 2023: N7 utilization <60%).Overseas-fab margin drag — Arizona/Japan/Germany are structurally costlier than Taiwan (the 1996 WaferTech precedent ran margins 20-25% lower); politically mandated capacity that dilutes returns.China ecosystem diffusion — SMIC licensing N+2/N+3 to Hua Hong/HLMC spreads the choke point; domestic 'good-enough' chips for inference/networking matter strategically even without matching TSMC.Lithography disruption — if Substrate's X-ray litho or xLight's FEL source industrializes, ASML's and TSMC's moats erode; low near-term probability, end-of-decade timeline.
Catalysts
Intel 18A / 18A-P HVM ramp (late 2026) and first external anchor customer — the swing factor for whether Intel Foundry survives as a #2 option.TSMC A16 (Super Power Rail) and N2 ramp — first GAA+backside-power volume for the leading pack; validates the 2nm paradigm.Smartphone demand cuts freeing N3 for AI — a 25% reallocation could yield ~0.7M more Rubins / ~1.5M more TPU v7s.Samsung/Intel design wins (Tesla AI5/AI6, Nvidia supply-chain entry) — foundry diversification under capacity scarcity and US political pressure.Substrate XRL tape-outs (as soon as 2028) — milestones that would 'silence the skeptics' on a credible ASML/TSMC disruptor.

Overview

Leading-edge logic is the most concentrated critical industry on earth. TSMC holds >90% of advanced-node capacity, and by SemiAnalysis's count 8 of the 10 largest companies in the world depend on it — roughly 3% of US GDP riding on one square mile in Tainan. The AI buildout has turned this from a smartphone business into an HPC business: HPC rose from ~33% of TSMC revenue in 2020 to 58% in 2025 while smartphone fell from ~48% to 29%, and Nvidia is modeled to consume more N3 wafers than Apple by 4Q27. That collision has produced 'the great AI silicon shortage' — every AI accelerator family is converging on N3 in 2026, pushing effective N3 utilization above 100%, with AI taking ~60% of N3 output in 2026 and 86% by 2027. Underneath the economics sits a physics inflection: FinFET is dead, so 2nm-generation nodes adopt gate-all-around (GAA) transistors and backside power delivery (BSPDN) — the first interconnect paradigm shift since copper in 1997 — but on different schedules: some nodes combine both (Intel 18A), while others do GAA first (TSMC N2) and add backside power in a later derivative (TSMC A16's Super Power Rail). The competitive field has thinned to TSMC (dominant), a process-competitive-but-broke Intel (first to GAA+BSPDN with 18A), a customer-starved Samsung, and Japanese startup Rapidus. China is a separate track: export controls froze SMIC out of EUV, yet its N+3 node reaches TSMC N6-class density (32.5nm metal pitch, tighter than Intel 18A's shipping 36nm) through brutal DUV multi-patterning — density it cannot translate into competitive power or cost. Cost-per-transistor scaling has nearly stopped (N3 delivered the weakest scaling in 50+ years), pushing value toward advanced packaging, chiplets, and DTCO, and inviting moonshots like X-ray lithography startup Substrate that could halve wafer cost if it works.

Positioning: Who Wins and Why

TSMC (TSM) — The dominant leading-edge foundry (>90% advanced-node share), sole viable N3/N2 supplier during the AI silicon shortage, kingmaker over allocation with pricing power. Two anchor tenants now (Apple + Nvidia). Cluster moat and cash-generating mature nodes fund the roadmap. Concentration risk in Taiwan is the flip side.

ASML — EUV/High-NA monopoly; every leading-edge wafer needs its tools ($225M each, >$650M wafers/yr). Litho spend intensity plateaus post-3nm, but the installed base and High-NA transition sustain it. Tail risk: a working X-ray litho (Substrate) or FEL source (xLight) could eventually erode the monopoly.

Deposition/etch/metrology WFE (Applied Materials, Lam, KLA, TEL) — As litho intensity plateaus after 3nm, share shifts to deposition, etch, metrology and packaging tools — exactly what GAA, backside power (CMP, fusion bonding, TSV etch) and 3D stacking demand most. Beneficiaries of the paradigm shift regardless of which foundry wins.

Intel Foundry (INTC) — high-risk turnaround — 18A defect density on-track and first to market with GAA+BSPDN (PowerVia); US-government backing and onshoring tailwind (any AI-capacity diversification toward Intel earns 'brownie points'). But the capital wall (needs 150k+ wafers/month, can't self-fund) and lack of an anchor tenant make it a speculative bet, not a sure thing.

GlobalFoundries (GFS) — specialty niche — Exited Moore's Law but leads in FD-SOI (22FDX/12FDX), RF/5G-6G, GaN-on-Si and silicon photonics — differentiated 'leading edge' insulated from the leading-edge capex arms race, with defense/US-industry partnerships. A structurally different, less capital-intensive profile.

Key Data

MetricValueNote
TSMC share of global advanced-node capacity>90%Over 90% of TSMC capacity and 87% of staff are in Taiwan; supplies ~70% of the world foundry (contract-manufacturing) market.
TSMC HPC vs smartphone revenue mix (2020→2025)HPC 33%→58%; smartphone 48%→29%The AI platform shift; Nvidia modeled to out-consume Apple at N3 by 4Q27.
AI share of TSMC N3 wafer output (2026→2027)~60% → 86%Effective N3 utilization exceeds 100% in 2H26; smartphone/CPU squeezed out.
Apple annual spend at TSMC (2014→2025)~$2B → $24B (12x)Apple went from 9% of TSMC revenue to a 25% peak; funded yield learning on every node since 20nm.
SMIC N+3 minimum metal pitch vs Intel 18A32.5nm vs 36nm (shipping)~10% tighter M0 than 18A Panther Lake, via SAQP DUV; 113.4 MTr/mm² Bohr density (>N6's 107.7).
N3 cost-per-transistor improvement vs N5~15% (best case)Weakest scaling for a major node in 50+ years; wafer spend up 38-55%, most designs get ~30% density.
N3B EUV layers vs N3E~25 → 19N3B nearly doubled N5's EUV count and yielded poorly; N3E relaxed pitches to cut cost, is the volume node.
SRAM bitcell size, N5 = N3E = Intel 18A (HD)0.021 µm²SRAM scaling is dead: N3E's HD cell identical to N5's; 18A HD cell also 0.0210 µm² on par with N5/N3E.
Backside power delivery benefit~15-20% power; up to ~25% cell shrink (direct backside contacts)First interconnect paradigm shift since aluminum→copper (1997); Intel 18A PowerVia first to HVM.
EUV tool economics$225M/tool → >$650M wafers/yrASML monopoly; High-NA EUV EXE:5000 ~$400M. Substrate X-ray litho targets ~$40M/tool.
TSMC 2022 capex 'gauntlet'$40-44B (70-80% on 2/3/5/7nm)Set a ceiling on Intel/Samsung's $25B+ plans; 10% on masks/advanced packaging (CoWoS, SoIC, InFO).
TSMC Arizona quarterly profit after Linde gas outage$140M → $1.4MImpure gas caused a multi-million-dollar scrap event; illustrates immature US supply-chain cluster.
TSMC N7 utilization trough (2023 downturn)<60% (from 100%)Foundry cyclicality: N7 below 70% in Q1'23, below 60% in Q2; even best-in-class N5 fell to ~88%.
HBM wafer intensity vs commodity DRAM~3x → ~4x at HBM4 (2026), even larger at HBM4EHBM crowds out commodity DRAM per bit; the memory shortage runs parallel to the N3 logic shortage.
Intel leading-edge fab capex requirement$25-30B per 10k wafers/week; needs 150k+/monthTSMC quoted ~$42B per 10k wafers/week for Arizona 3nm; Intel core business ~breakeven, can't self-fund.
TSMC advanced packaging CoWoS revenue (2025)$9.6B (2.5x InFO)CoWoS grew from $0.6B (2018) to $8.4-9.6B (2025), 14x; advanced packaging now >10% of TSMC revenue.
Huawei prime-core frequency roadmap (LogicFolding)2.75 GHz (2025) → ~5 GHz (2031)Via 3D active-logic stacking, not planar scaling; claims '14A-equivalent' density per package footprint by 2031.
Intel 2026 capital raise & balance sheetraised ~$20B (US gov 433M shares @$20.47, SoftBank @$23.00, Nvidia @$23.28); bought back Apollo's 49% of Fab 34 for $14.2B (~$7.7B cash + $6.5B bridge); net debt ~$51.5B; a 4-5% dilution would add ~$25BFunding the foundry turnaround under CEO Lip Bu Tan and a rebuilt board (Intel Should Raise Capital, SemiAnalysis).
Intel Foundry / product demand wins (2026)Nvidia DGX Rubin NVL8 lists dual Intel Xeon 6 host CPUs; Google signed a multiyear Xeon + custom-IPU dealExternal validation for Intel Foundry / product (Intel Should Raise Capital, SemiAnalysis).

Key Theses

1. One square mile in Taiwan carries ~3% of US GDP — the most extreme concentration risk in the global economy.
Over 90% of TSMC capacity and >90% of global advanced-node output sit in Taiwan. 8 of the world's 10 largest companies depend on TSMC (the 9th is TSMC), and more than a third of their combined $2T revenue rides on TSMC hardware. SemiAnalysis frames onshoring as a security imperative: the 2021 shortage of *mature* chips cost ~1% of US GDP ($240B); zeroing out advanced logic would be 'a 100-foot tsunami.'
“That alone is 3% of U.S. GDP dependent on 1 square mile in southern Taiwan… The world economy would grind to a halt without TSMC.”— TSMC Overseas Fabs – A Success? (2025-12-01), SemiAnalysis
2. AI turned TSMC from a smartphone company into an HPC company — and Nvidia will out-consume Apple at N3 by 4Q27.
HPC revenue at TSMC rose from ~33% (2020) to 58% (2025) while smartphone fell from ~48% to 29%. Apple, TSMC's decade-long anchor, has been consistently >50% of node launches since 20nm (near-100% in some cases, e.g. N3) and funded the yield learning curve of every node; now Nvidia's AI cash makes it a second anchor. SemiAnalysis models Nvidia consuming more N3 wafers than Apple by 4Q27, and Apple's share of N2 dropping to 48% — the first time in a decade Apple isn't the dominant customer on a new node — because A16 is architected for HPC (backside power, GAA) and smartphones skip it.
“Our model shows Nvidia will consume more N3 wafers than Apple by 4Q27. Apple's share of N2 drops to 48%, the first time in a decade Apple is not the dominant customer on a new node.”— Apple-TSMC: The Partnership That Built Modern Semiconductors (2026-01-08), SemiAnalysis
3. The 'great AI silicon shortage' is now front-end wafers: every accelerator converges on N3 in 2026, pushing utilization past 100%.
After CoWoS and power were the binding constraints, TSMC N3 logic capacity is now the choke point. Nvidia (Blackwell→Rubin), AMD (MI350/MI400), Google TPU v7, AWS Trainium3 and Meta MTIA all move to N3 in 2026. AI takes just under 60% of N3 output in 2026 and 86% by 2027, nearly squeezing out all smartphone/CPU wafers. Effective N3 utilization exceeds 100% in 2H26; TSMC is constrained by cleanroom space, so gains for one customer mean another loses allocation.
“We model AI demand to be 86% of 2027 N3 wafer output nearly entirely squeezing out smartphone and CPU wafers.”— The Great AI Silicon Shortage (2026-03-12), SemiAnalysis
4. 2nm-generation logic requires two simultaneous paradigm shifts — GAA transistors and backside power — the biggest transition in decades.
FinFET cannot scale further and SRAM shrink is dead, so leading-edge logic must adopt GAA and BSPDN in 2-3 years. BSPDN is the first interconnect innovation since aluminum→copper in 1997; it delivers ~15-20% power improvement and enables sub-6T cells. Foundries diverge on aggressiveness: Intel 18A ships PowerVia first (easier, less scaling); TSMC A16 and Samsung SF2Z dive into higher-risk direct backside contacts. This inflection is the rare opening that could force Samsung or Intel out — or let in Rapidus.
“Leading-edge logic must adopt two new paradigms in the next 2-3 years: gate all around (GAA) and backside power delivery.”— Clash of the Foundries: Gate All Around + Backside Power at 2nm (2024-10-01), SemiAnalysis
5. SMIC N+3 reaches TSMC N6-class density without EUV — but density it cannot turn into competitive power or cost.
SemiAnalysis's STEEL lab teardown of Huawei's Kirin 9030 measured a 32.5nm minimum metal pitch on SMIC N+3, ~10% tighter than the 36nm shipping in Intel 18A Panther Lake, and 113.4 MTr/mm² Bohr density (just above N6's 107.7). But it's achieved via SAQP quadruple-patterning DUV and DTCO, so it costs far more and yields less. The chip performs like a 3-year-old Android flagship: Apple's efficiency core delivers 20% more integer performance at 1W vs Huawei's prime core at 4.5W.
“SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost.”— Is SMIC N+3's Metal Pitch Smaller than Intel 18A's? (2026-06-14), SemiAnalysis
6. Apple built TSMC as much as TSMC built Apple — a $10B 'bet the company' gamble that reshaped computing.
In 2013 Morris Chang committed $10B to 20nm on Apple's promise; the A8 (2014) proved it. Apple's TSMC spend grew from ~$2B (2014) to $24B (2025) — 12x in 11 years — going from 9% of TSMC revenue to a 25% peak, funding the yield learning curve of every node since 20nm. Intel's Otellini declined the same deal over margins: SemiAnalysis calls it 'the biggest misstep in the history of chip foundries.' Vertical integration paid off — Mac gross margin expanded ~11pp after dropping Intel.
“I bet the company, but I didn't think I would lose.”— Apple-TSMC: The Partnership That Built Modern Semiconductors (2026-01-08), SemiAnalysis
7. Cost-per-transistor scaling has nearly stopped: N3 delivered the weakest scaling in 50+ years.
N3's total spend per wafer-start rose 38-55% vs N5 (N3E pricing ~35% above N5), with density up ~56% only in the best FinFlex config — an ~15% cost-per-transistor improvement, the weakest ever for a major node. Most designs get ~30% density, implying flat-to-negative cost scaling. N3B had ~25 EUV layers (nearly double N5); N3E cut that to 19 for cost. SRAM barely scaled (N3B 6T cell only 5% smaller vs the promised 20%). Result: an explosion of chiplets and advanced packaging.
“This results in an ~15% cost per transistor improvement, the weakest ever scaling for a major process technology in 50+ years.”— TSMC's 3nm Conundrum, Does It Even Make Sense? (2022-12-21), SemiAnalysis
8. Intel Foundry has the process (18A on track) but not the cash — it needs 150k+ wafers/month and can't self-fund the fabs.
18A defect density is on-track and Intel will be first to market with GAA+BSPDN (PowerVia), a genuine bright spot. But Intel needs $25-30B capex per 10k wafers/week and 150k+ wafers/month to be competitive, at a time its core business is barely breakeven. TSMC's mature nodes throw off cash to fund the leading edge; Intel historically deprecated old nodes and has no such 'forever node' cash pool. It has ~$120B of capital to tap but may need more — 'we are not sure where they can get this cash from.'
“Building 150,000+ wafers a month of leading edge capacity requires a lot of investment… Today they cannot afford to build these fabs with their own cashflow.”— Is Intel Back? Foundry & Product Resurgence Measured (2024-04-02), SemiAnalysis
9. TSMC's overseas fabs are real but structurally costlier — Chang cites the 1996 WaferTech precedent, whose margins ran 20-25% below Taiwan.
Arizona, Japan (JASM) and Germany (ESMC) all yield wafers, but the cluster can't be replicated: 90%+ of TSMC capacity and 87% of staff remain in Taiwan; US permitting takes ~2x as long; the supply chain isn't there (a Linde gas outage caused a multi-million-dollar scrap event, cutting one quarter's AZ fab profit from $140M to $1.4M). The 1996 WaferTech venture ran 20-25% lower margin on identical products — a precedent Chang cites. Arizona remains a small single-digit share of leading-edge output and won't materially cut Taiwan dependence in the near term.
“I think it will be a very expensive exercise in futility.”— TSMC Overseas Fabs – A Success? (2025-12-01), SemiAnalysis
10. The next lithography war could be won outside ASML: X-ray litho startup Substrate claims 50% cheaper wafers.
The industry is ripe for disruption (ASML admits its own hyper-NA roadmap 'may not be economically viable'). Substrate's X-ray litho tool claims single-patterning at 2nm/1nm, high-NA-class resolution, 12nm features, <1.6nm overlay — at a tool cost ~$40M vs High-NA EUV's $400M. SemiAnalysis's model is skeptical of the full 50% claim (its own analysis shows ~25% cost reduction) but even that is 'massive.' Combined with xLight's free-electron-laser source, these are the first credible threats to on-shore the litho monopoly — with China running parallel efforts.
“Substrate promises the same great taste but without $400M in calories.”— How to Kill 2 Monopolies with 1 Tool (2025-10-29), SemiAnalysis
11. Samsung Foundry's decline is cultural, not just technical — it lied about yields and lost its two biggest customers.
Samsung was technically first to GAA (SF3E, 2022) but only in a low-volume bitcoin/watch chip. Its 4LPE node yielded as low as ~20% (parametric), Exynos 2200 GPU clocks were cut from 1.69GHz to 1.29GHz, and Korean media reported the foundry lied about 5/4/3nm yields to customers and its own chairman. Qualcomm and Nvidia both fled to TSMC; both negotiated to pay per yielded die rather than per wafer. SemiAnalysis: TSMC's N3 yield issues (TSMC still 80%+ vs Samsung's 30-40%) don't mean Samsung can catch up — 'you are sorely mistaken.'
“The foundry is even allegedly lying about the yields… lied to customers and the Samsung chairman on 5nm, 4nm, and 3nm yields.”— Samsung Electronics Cultural Issues Are Causing Disasters In Samsung Foundry (2022-04-17), SemiAnalysis
12. China's chip choke point is shifting from one fab to an ecosystem — SMIC is being forced to license N+2/N+3 to peers.
Export controls changed China's optimization problem rather than ending it. SMIC is licensing N+2/N+3 to HLMC/Hua Hong at government direction, and the process learning could feed Ascend AI accelerators, Alibaba's T-Head, and Cambricon (a likely ByteDance supplier). Peking University even built a prototype EDA tool for Huawei's LogicFolding. Once manufacturing knowledge spreads, sanctions aimed at SMIC alone lose bite. 'If domestic chips become good enough for phones, inference, networking… they can matter strategically without matching TSMC.'
“Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses.”— Is SMIC N+3's Metal Pitch Smaller than Intel 18A's? (2026-06-14), SemiAnalysis
13. Advanced packaging, not lithography, is now where value and constraint migrate — CoWoS is 2.5x InFO and stacking is the future.
With cost-per-transistor scaling stalled, TSMC's packaging platforms carry the growth. CoWoS revenue hit $9.6B in 2025, 2.5x Apple's InFO ($3.5B+), fueled by Nvidia/AMD HBM. Apple (InFO-PoP) and Nvidia (CoWoS-L) don't compete for packaging lines today, but converge on 3D SoIC/hybrid bonding by AP6/AP7. WFE litho spend intensity plateaus after 3nm; share shifts to deposition, etch, metrology and packaging tools. SemiAnalysis: 'packaging is now a key avenue for driving compute scaling.'
“CoWoS revenue hit $9.6B in 2025, 2.5x InFO, fueled by Nvidia and AMD demand.”— Apple-TSMC: The Partnership That Built Modern Semiconductors (2026-01-08), SemiAnalysis

Article Deep-Dives

Is SMIC N+3's Metal Pitch Smaller than Intel 18A's? (STEEL teardown of Huawei Kirin 9030) (2026-06-14)
The first public report from SemiAnalysis's own Oregon teardown lab (STEEL), physically reverse-engineering Huawei's Kirin 9030 on SMIC N+3 against a MediaTek Helio G99 on TSMC N6. Headline finding: SMIC N+3 hits a 32.5nm minimum metal pitch — ~10% tighter than Intel 18A Panther Lake's shipping 36nm M0 — and 113.4 MTr/mm² Bohr density, edging TSMC N6. But it's a cherry-picked metric: N+3 gets there via SAQP quadruple-patterning DUV (M0 below single-DUV resolution), COAG, single diffusion break and a 3:2 M1-to-gate ratio, all adding masks, overlay error and cost. Performance lags a 3-year-old flagship (Apple's efficiency core: +20% integer at 1W vs Huawei's prime at 4.5W). SMIC has scaling levers left (theoretical N+4 ~138 MTr/mm² = N5-class, N+5 via backside contacts ~164 = 18A-class) but each is harder and more expensive. Huawei's answer to no-EUV is the 'τ scaling law' / LogicFolding — 3D-stacked active logic targeting ~5GHz and '14A-equivalent' density by 2031, a packaging roadmap not a foundry one.
Apple-TSMC: The Partnership That Built Modern Semiconductors (2026-01-08)
A five-phase history and forward model of the most consequential partnership in chips. Built on SemiAnalysis's proprietary Foundry and Apple Wafer Demand models: Apple's TSMC spend grew 12x ($2B→$24B) in 11 years — consistently >50% of node launches since 20nm (near-100% in some cases, e.g. N3), funding the yield learning curve of every node. TSMC itself grew 9.4x ($13B→$122B revenue), capex 7x, gross margin +13.5pp to 59%+. Phases run from Intel's 2010 rejection (Otellini's 'biggest misstep in foundry history') through mutual lock-in (Samsung 3nm yields 30-40% vs TSMC 80%+; switching cost $2-5B) to today's 'diversified dependence,' where Nvidia becomes TSMC's second anchor and Apple's N2 share drops to 48%. Also maps Apple's 5 transformational acquisitions ($278M P.A. Semi → A4; Intel modem $1B), 8,000+ engineers across 15 design centers, and the packaging bifurcation (Apple InFO vs Nvidia CoWoS, converging at 3D SoIC by AP6/AP7). Apple's real diversification isn't leading-edge — it's PMICs, display drivers, CIS (a new Samsung Austin deal), and a possible Intel 18A-P base-M-series qualification.
Clash of the Foundries: Gate All Around + Backside Power at 2nm (2024-10-01)
The definitive technical primer on the 2nm-generation inflection. FinFET is exhausted and SRAM shrink is dead, so all four foundries must adopt GAA transistors and backside power delivery (BSPDN) in 2-3 years — the first interconnect paradigm shift since aluminum→copper (1997), worth ~15-20% power. Deep-dives the three BSPDN schemes: buried power rail (simplest but contaminates FEOL, won't reach HVM), Intel's PowerVia (easier, self-aligned, less scaling), and direct backside contacts (highest risk, ~25% cell shrink, needs <5nm post-bond overlay and ~50nm-pitch backside patterning). Roadmaps diverge: Intel 18A first to GAA+BSPDN (PowerVia) but at ~3nm-class density; TSMC N2 is GAA-only, A16 adds conservative backside contacts (7-10% density); Samsung SF2Z in 2027; Rapidus a heavily-subsidized long shot (IBM 2nm license, 25k wpm, no BSPDN, no signed volume customers). SRAM 'beating a dead horse' — the ~22% N2 gain is periphery, not bitcell.
The Great AI Silicon Shortage (2026-03-12)
The constraint has moved down the stack: from CoWoS packaging, to datacenter power, and now to front-end wafers themselves. Every AI accelerator family converges on TSMC N3 in 2026 (Nvidia Blackwell→Rubin, AMD MI350/MI400, Google TPU v7, AWS Trainium3, Meta MTIA) plus Vera CPUs, NVLink6 and Tomahawk6 switches. AI takes just under 60% of N3 output in 2026, rising to 86% in 2027, nearly squeezing out smartphone/CPU. Effective N3 utilization exceeds 100% in 2H26; TSMC is gated by cleanroom space, so one customer's gain is another's loss — TSMC acts as 'kingmaker,' prioritizing high-ASP, multi-year-visibility AI over saturated mobile. Smartphones are the 'release valve': reallocating 25% of smartphone N3 starts could yield ~0.7M more Rubins or ~1.5M more TPU v7s. Memory is the parallel shortage: HBM consumes ~3x commodity DRAM wafers per bit, and DDR margins have surged to rival HBM, removing suppliers' incentive to add HBM capacity.
How to Kill 2 Monopolies with 1 Tool (Substrate X-ray lithography) (2025-10-29)
SemiAnalysis surfaces Substrate, a Bay Area startup building an X-ray lithography (XRL) tool that could break both ASML's litho monopoly and TSMC's foundry dominance. Claims: single-patterning at 2nm/1nm/beyond, high-NA-class resolution, 12nm features, <1.6nm overlay, 0.25nm CDU — at a tool cost ~$40M vs High-NA EUV's $400M, promising 50%-cheaper wafers. SemiAnalysis is rigorously skeptical (its own model shows ~25%, not 50%) but concludes external reports say 'the litho tool is legit.' If real, it opens process design flexibility, eliminates multi-patterning, and threatens a >$200B TSMC-share TAM by 2030. The article catalogs the monumental non-litho challenges (stochastic defects, secondary-electron blur, HAR etch, X-ray damage) and contrasts Substrate (novel exposure tool, own fab) with xLight (free-electron-laser source that plugs into existing EUV). Framed as a US strategic imperative — 'seven American mega-caps depend almost completely on TSMC Taiwan for nearly $2T' — with China running parallel FEL/synchrotron/XRL efforts.
TSMC Overseas Fabs – A Success? (Arizona / Japan / Germany economics) (2025-12-01)
A candid audit of TSMC's three overseas ventures and why the Taiwan cluster is so hard to replicate. Over 90% of capacity and 87% of staff remain in Taiwan; the Hsinchu/Taichung/Tainan 'one-hour ecosystem' — TSMC can obtain anything it needs within an hour — is the structural moat. Arizona has ramped — early yield reportedly ~4pts above comparable Taiwan fabs — but on a mature 4nm process already optimized for 2+ years, with an easy high-yield product mix (AMD chiplets, Apple SoCs ~100mm² vs Nvidia ~800mm² reticle GPUs in Tainan). The supply chain isn't there: a Linde gas outage caused a scrap event that cut quarterly AZ profit from $140M to $1.4M; US permitting takes ~2x Taiwan's. The 1996 WaferTech precedent ran 20-25% lower margin ('a nightmare fulfilled,' per Chang). JASM (Japan, 28/16nm, Sony) and ESMC (Germany, 28/16nm, Bosch) are legacy-focused; a UAE fab was floated then killed over sovereign-control and IP-leak concerns. TSMC's $165B US commitment may reach 12 Arizona phases by the 2030s — the world's largest advanced fab — if the cluster can be built.

Reference: Value Chain

Leading-edge logic foundryTSMC (dominant), Samsung Foundry, Intel Foundry, Rapidus (startup), SMIC (China) — Manufactures the most advanced digital logic (N5/N3/N2, 18A). TSMC holds >90% of advanced-node capacity; the others are customer-challenged or years behind. This is where the AI accelerator, CPU and networking silicon is physically made.
▼
Fabless designers (anchor customers)Apple, Nvidia, AMD, Qualcomm, MediaTek, Broadcom, Google/AWS/Meta (custom ASIC), HiSilicon (China) — Design chips and buy wafers; the largest fund each node's learning curve. Apple anchored TSMC for a decade; Nvidia is now a second anchor. Their node choices and prepayments (Nvidia alone >$3B) dictate what capacity TSMC builds.
▼
Lithography & wafer fab equipment (WFE)ASML (EUV/High-NA monopoly), Applied Materials, Lam Research, KLA, Tokyo Electron; challengers xLight, Substrate — Supplies the tools. ASML's EUV monopoly ($225M/tool) is the choke point. Post-3nm, litho spend intensity plateaus and share shifts to deposition/etch/metrology and packaging tools. Startups (Substrate X-ray litho, xLight FEL source) aim to break the cost curve.
▼
Advanced packaging & 3D integrationTSMC (CoWoS, InFO, SoIC), Intel (EMIB, Foveros, EMIB-T), OSATs (ASE/SPIL, Amkor) — As transistor scaling stalls, value migrates here. CoWoS ($9.6B in 2025, 2.5x InFO) enables Nvidia/AMD HBM integration; InFO powers Apple SoCs; SoIC/hybrid bonding is the 3D future. Now often the binding constraint on AI accelerator output alongside front-end wafers.
▼
Specialty & mature nodes (the cash engine)TSMC (N28, JASM/ESMC), GlobalFoundries (FD-SOI, silicon photonics, GaN), SMIC/Hua Hong (China) — Fully-depreciated older fabs (equipment lasts far beyond the 5-year accounting life) throw off the cash that funds leading-edge expansion. GlobalFoundries exited Moore's Law but leads in FD-SOI, RF, GaN-on-Si and silicon photonics — a different kind of 'leading edge.'

Reference: Core Concepts

Process node (N5 / N3 / N2 / A16). A named generation of transistor manufacturing. Names ('3nm', '2nm', A16=1.6nm) are marketing, not physical dimensions; what matters is contacted gate pitch, metal pitch, cell height and resulting density/power/performance (PPA). Each family spawns many variants (N3B, N3E, N3P, N3X, N3S) tuned for cost, mobile, or HPC.

FinFET → GAA (Gate-All-Around). FinFET (fins the gate wraps on 3 sides) has scaled since 22nm but can no longer improve. GAA stacks horizontal 'nanosheets' so the gate surrounds the channel on all 4 sides, boosting drive current. All 2nm-generation nodes (TSMC N2, Intel 18A, Samsung SF2) adopt GAA 2025+. Successors: forksheet (denser, worse electrostatics) and CFET (stacking N over P for ~1.5x scaling, but ~a decade from HVM).

Backside Power Delivery (BSPDN). Moving power wiring to the wafer backside, freeing the frontside entirely for signals — the first interconnect innovation since aluminum→copper (1997). Enables cells shorter than 6-track (~15% density) and cuts power ~15-20%. Three flavors: buried power rail (simplest, contamination risk, won't reach HVM), Intel's PowerVia (easier, less scaling), and direct backside contacts (highest risk/reward, ~25% cell shrink, needs <5nm post-bond overlay). TSMC calls its HPC version 'Super Power Rail.'

EUV vs DUV multi-patterning. Extreme UV (13.5nm) prints tiny features in one shot; a single EUV tool costs $225M and can produce >$650M of wafers a year. Deep UV (193nm immersion) must use SADP/SAQP multi-patterning (2 or 4 passes) to hit the same pitch, adding masks, overlay error, complexity and cost. Export controls deny China EUV, forcing SMIC into aggressive DUV multi-patterning.

DTCO & the death of SRAM scaling. Design-Technology Co-Optimization: squeezing density from layout/design tricks (fin depopulation, contact-over-active-gate, single diffusion break) rather than raw lithography. Increasingly the main scaling lever because SRAM bitcells have barely shrunk since N5 — N3E's 6T cell (0.021µm²) is identical to N5's. Logic keeps scaling; cache does not, raising the importance of architecture and 3D stacking.

Anchor tenant / 'first and best' customer. A leading-edge fab needs one huge, deep-pocketed customer to pre-fund capacity and prove out yield/IP on each new node. Apple was TSMC's anchor for a decade (funded the learning curve, often >50% and near-100% of node launches). AI's cash now gives TSMC a second anchor in Nvidia. Intel Foundry's core problem: no anchor tenant to fill and de-risk its leading-edge fabs.

Cluster effect / 'one-hour ecosystem'. TSMC's structural moat: Hsinchu/Taichung/Tainan science parks put semiconductor firms, suppliers and talent within an hour, so anything needed arrives fast and yield problems are solved 24/7. Over 90% of TSMC capacity and 87% of staff are in Taiwan. This cluster cannot be cheaply replicated abroad — the core reason Morris Chang called the Arizona fabs 'a very expensive exercise in futility.'

STCO / 3D stacking (Huawei's answer to no-EUV). System-Technology Co-Optimization: when you can't shrink transistors, shorten wires and stack active logic vertically. Huawei's 'τ (tau) scaling law' and 'LogicFolding' split a logic block across face-to-face bonded dies so the bond behaves like an extra metal layer, recovering frequency and density. Density claimed 'per package footprint' is not comparable to a foundry's per-mm² number.

Open Questions

Sources (SemiAnalysis)

Independence & sourcing. This is independent analysis by Yicheng Yang, distilled from publicly accessible SemiAnalysis articles (free posts and free previews; no paywall circumvention) and verified against the underlying text. It is not affiliated with, endorsed by, or a substitute for SemiAnalysis — subscribe there for the full research. All referenced claims are sourced and linked per SemiAnalysis's attribution terms. No SemiAnalysis images are reproduced. Nothing here is investment advice.