AI Supply Chain Research · Sector 05

Semiconductor Equipment

The picks-and-shovels of AI: whoever owns EUV, etch, deposition and metrology owns the physical bottleneck of Moore's Law — and, increasingly, the cost curve is decided by process tricks, not just by ASML's next scanner.  ·  ← back to the series  ·  Background: Primer §00, §01, §02, §06, §09, §10

At a glance
Winners
ASMLApplied Materials (AMAT)Lam Research (LRCX)Tokyo Electron (TEL)KLAKokusai ElectricEnablers: Veeco, EV Group, BE Semi, Lasertec, JSR, Entegris
Bottlenecks
EUV source power — CO2-laser-on-tin-droplet EUV tops out; dose requirements outrun ASML/Trumpf's power roadmap, capping throughput and forcing multi-patterning or DSA.EUV mask ecosystem — the 6"x6" reticle standard (since the 1980s) and actinic mask inspection are chokepoints; a larger 6x12" mask needs the whole blank/write/inspect chain rebuilt.HAR etch depth — 6-7 micron / 70:1 channel-hole wall limits NAND vertical scaling; cryo etch and string-stacking are the only ways up.Fixed-cost explosion — $40M 3nm mask sets + verification (Intel's 12 Sapphire Rapids steppings) restrict the leading edge to high-volume designs.
Risks
WFE cyclicality — a memory glut (2022-23 NAND utilization ~60%) or fab-buildout delays (TSMC/Intel/Samsung push-outs) can cut equipment revenue sharply and quickly.High-NA over-investment — being too early with a billion-dollar fleet on a technology that's not yet cheaper than low-NA (Intel's bet) could be as damaging as being late.China substitution + export-control blowback — SMEE/AMEC/Naura rising at trailing edge; controls that only cover ArFi leave DUV/resist/service holes, and cut off a huge China TAM for Western toolmakers.Value migration mis-bet — backing the wrong patterning path (High-NA vs multi-patterning vs Sculpta vs DSA vs MOR/dry resist) strands R&D and capacity.
Catalysts
AI capex super-cycle — hyperscaler datacenter/AI spend drives leading-edge logic + HBM/DRAM WFE; larger dies and more designs lift both advanced and trailing WFE.GAA + 3D DRAM ramp — nanosheet logic and 3D DRAM sharply raise ALD/etch intensity, reshuffling deposition/etch share (Kokusai, ASMI, Lam, TEL, AMAT).2025 memory shortage — the 2023-24 NAND glut + capex delays set up a sharp WFE recovery as supply/demand rebalance.6x12" mask decision + High-NA/DSA insertion at 14A/A10 — an ASML commitment to large masks, or Intel proving High-NA+DSA economical, would re-rate the whole litho roadmap.

Overview

Wafer fabrication equipment (WFE) is a ~$100B/year oligopoly split by process step, not by node. ASML holds a hard monopoly on EUV lithography (each low-NA tool >$200M, each High-NA EXE:5000 ~$400M and 150 metric tons); Applied Materials and Lam Research dominate deposition and etch; Tokyo Electron owns 100% of EUV photoresist coat/develop tracks; KLA owns process control. SemiAnalysis's core, repeated, non-consensus thesis is that lithography is NOT destiny: as 2D scaling dies, value migrates from the scanner to complementary patterning (AMAT Sculpta pattern-shaping, directed self-assembly, metal-oxide/dry resist) and to etch+deposition-driven vertical scaling (3D NAND, gate-all-around, 3D DRAM). Their most contrarian call — that High-NA EUV single-patterning is actually MORE expensive than low-NA double-patterning through the 1nm node — cuts directly against ASML's marketing and reframes the whole roadmap around cost-per-wafer, not resolution. The memory downturn/AI-driven upturn cycle, Chinese equipment substitution, and export-control gaps are the macro overlay.

Positioning: Who Wins and Why

ASML — Absolute EUV/High-NA monopoly and DUV leader — the hardest bottleneck in tech. But the SemiAnalysis nuance is a double-edge: High-NA ramp is slower and less economic than guided, and a customer-friendly 6x12" mask (which ASML resists because 2 normal tools = more revenue) is the swing factor. Own the moat, discount the guidance.

Applied Materials (AMAT) — #2 in WFE and the broadest portfolio (deposition, etch, PVD, implant, plus Sculpta pattern shaping and panel-level packaging PVD). Structurally positioned for the value migration away from pure litho toward materials-engineering and vertical scaling; Sculpta is a new litho-adjacent TAM.

Lam Research (LRCX) — HAR-etch and deposition leader — the engine of 3D NAND/DRAM vertical scaling — plus the dry-resist disruptor (~$1.5B target, above-corporate margin). Risk: TEL cryo etch + moly change contest >$1B of NAND. Malaysia offshoring lifts gross margin.

Tokyo Electron (TEL) — 100% of EUV coat/develop tracks (~$5B+ run-rate monopoly), a strong batch-ALD #2, and the cryo-etch/moly challenger poised to take NAND share from Lam. Defends resist via wet-develop innovation; JSR/Inpria alliance backs MOR.

KLA — Dominant in process control/metrology — a toll booth on every fab across 1000+ steps, rising with complexity. Watch the AI/virtual-metrology headwind (Lynceus-type) to sampling capex, but the moat in physical inspection is deep.

Kokusai Electric — Hidden batch-ALD monopoly (~70%), process-of-record at all top-5 NAND makers, TAM growing with GAA. AMAT's aborted $3.5B buyout (a $2.2B offer raised 59%, then abandoned after two years awaiting China antitrust approval) is the third-party validation of the moat.

Enablers: Veeco, EV Group, BE Semi, Lasertec, JSR, Entegris — Niche monopolies riding 3D/heterogeneous integration: Veeco (EUV mask-blank deposition, laser anneal, GaN); EV Group/BE Semi (wafer/hybrid bonding); Lasertec (actinic EUV mask inspection); JSR/Entegris (resist & materials).

Key Data

MetricValueNote
Low-NA EUV tool price>$200M (NXE:3800E)Cost per wafer is dominated by throughput, so the whole High-NA cost debate turns on this.
High-NA EUV tool price / weight~$400M / 150 metric tons (EXE:5000)~2x a low-NA tool; depreciates >$150,000/day.
High-NA vs low-NA single-exposure cost~2.5x (IBM SPIE data)So High-NA only wins where it replaces 3+ low-NA masks; 4-mask SALELE is 1.7-2.1x a single High-NA pass.
Lithography share of a 3nm node cost~35%The prize everyone wants to shrink via pattern shaping / DSA / vertical scaling.
High-NA source power at first shipment110% of targetFirst EUV system ever to exceed initial target (vs NXE:3300 at 15%, NXE:3400B at 50%); reliability ~85%.
Intel High-NA wafers exposed30,000 across 2 EXE:5000 toolsIntel is years ahead; TSMC/Samsung only ordered R&D tools. Overlay 0.6nm to a low-NA tool.
6x12" mask throughput uplift+23-50%Would eliminate High-NA stitching and swing economics — but ASML says only 'early next decade,' and 2 normal-mask tools = $200-300M more ASML revenue.
Sculpta per-layer savings~$250M capex / 100k WSPM + ~$50/wafer opexAMAT's claim vs adding an EUV loop; potential ~$4.5B EUV demand reduction at full adoption.
3D NAND density / cost-per-bit scaling+30%/yr density, -21%/yr cost/bitSince 2013; slowing to low-to-mid-teens cost decline as HAR etch hits the 6-7 micron / 70:1 wall.
Kokusai batch-ALD share~70% (batch ALD); ~46% (all batch deposition)AMAT tried to buy it for $3.5B (raised 59%) before China antitrust blocked it.
TEL EUV coat/develop track share100%; ~$5B+ annual run-rateMonopoly on the track around every ASML tool, pulling in adjacent etch/clean wins.
Lam dry-resist revenue target~$1.5B over 5 yrs; multi-$B by decade endHigher gross margin than Lam's ~46% corporate average; JSR bought Inpria for $514M to defend MOR.
NIL mask lifetime vs photomask~50 wafers vs >100,000The defectivity killer; NIL throughput ~100 wph (4-cell) vs 220 (EUV)/330 (DUV).
3nm mask set cost~$40M (vs >$10M at 7nm, >$1M at 28nm)Fixed-cost explosion; a leading-edge chip tape-out runs $50-75M all-in at 7nm.
Lynceus AI process-control gains90% faster defect detect (4d to 3h); 4x less samplingIn two HVM fabs; a structural headwind to metrology sampling capex.
Lam Malaysia manufacturing shift>1/3 of future capacity; +50% total footprint (~845k sq ft)Cost-driven offshoring of high-value tool manufacturing from the US.
ASML 2030 revenue / WFE market$44-60B ASML implies ~$150-280B WFESemiAnalysis: guidance is optimistic and bakes in 10-20% 'inefficient' regionalized capacity.

Key Theses

1. High-NA EUV single-patterning is MORE expensive than low-NA double-patterning — all the way through the 1nm node.
Dose requirements rise exponentially as critical dimension shrinks. Low-NA double-patterning splits a layer into two exposures with ~2x-larger features each, sitting far down the exponential dose curve, so the scanner runs at full stage-limited throughput. High-NA single-exposure is dose-limited even at a hypothetical 1kW source. The throughput advantage is so strong that despite 2x the wafer passes, low-NA double-patterning is cheaper. IBM's own SPIE data confirmed it: a single High-NA exposure costs ~2.5x a single low-NA exposure, so High-NA only wins when it replaces 3+ low-NA masks (e.g. 4-mask SALELE).
“Our lithography models show that despite reducing complexity, high-NA EUV single patterning costs significantly more than double-patterning using existing low-NA machines for upcoming technology nodes including 1.4nm/14A.”— ASML Dilemma: High-NA EUV is Worse vs Low-NA EUV Multi-Patterning (2023-12-11), SemiAnalysis
2. Lithography is not destiny — as 2D scaling dies, value migrates from ASML's scanner to complementary patterning and to etch/deposition-driven vertical scaling.
NAND broke the mold in 2013: it stopped relying on lithography and went vertical, so density improved ~30%/year and cost/bit fell ~21%/year while the value shifted to HAR etch and ALD. NAND litho-intensity is only ~10-12% of WFE. The same physics now hits logic (GAA nanosheets, then CFET) and DRAM (3D DRAM), raising etch/deposition intensity. The inflection to 'stacking not shrinking' is exactly where SemiAnalysis places High-NA's natural, cost-effective insertion — the 2030+ 1nm/7A era, not 14A.
“This is because NAND flipped the formula and stopped relying on lithography for patterning smaller cells. Instead, NAND has relied on a different architecture, 3D NAND... density has improved by 30% per year at a very consistent rate.”— NAND Flash Monopoly Broken? Tokyo Electron Moly Dep + Cryo Etch Takes On Lam Research (2023-07-16), SemiAnalysis
3. Applied Materials' Sculpta 'pattern shaping' is real, works, and could cut EUV double-patterning demand by ~$4.5B — not the immature science project critics dismissed.
Sculpta fires a highly directional angled ribbon-beam plasma (beam angle controllable 0-70 degrees) to elongate a feature on one axis after a single exposure, replacing a second litho pass for tight tip-to-tip, corner-to-corner via, and stochastic-defect repair (>90% defect reduction). AMAT claims per-layer savings of ~$250M capex per 100k wafers/month and ~$50/wafer opex versus adding an EUV loop. It's not vaporware: AMAT has published since 2015, the first customer engaged in ~2017, and it inserts on a 2nm-class node in late-2024/2025. But it can't be used everywhere — it shapes existing features, it doesn't add routing density.
“According to Applied Materials, the Sculpta tool could be used to reduce the use of EUV lithography by as much as HALF for some layers. If true, this would reshape the cost structure of the industry.”— EUV Requirements Halved? Applied Materials' Sculpta Redefines Lithography And Patterning (2023-03-06), SemiAnalysis
4. Directed Self-Assembly (DSA) is Intel's 'magic bullet' — the only thing that could make High-NA economical at 14A by cutting EUV dose 50%+.
Because High-NA's cost problem is the exponential dose-vs-CD curve, the fix is to relax the EUV exposure and 'heal' it. DSA block copolymers (PS-b-PMMA) self-assemble into ~9nm lines aligned to a coarse, low-dose EUV guide pattern; they align to the average of the guide, so the guide's line-edge roughness can be poor. That relaxes dose by 50%+ (Intel R&D shows 25 mJ/cm2 = a 3-4x cut). This is why Intel — alone among chipmakers — bet on High-NA in HVM at 14A while TSMC/Samsung ordered only R&D tools. The catch: DSA has been stuck in research for a decade because of defectivity risk.
“Relaxing image quality requirements for the EUV exposure means the dose can be reduced by 50% or more.”— Intel's 14A Magic Bullet: Directed Self-Assembly (DSA) (2024-04-18), SemiAnalysis
5. The NAND monopoly is breakable: Tokyo Electron's cryogenic HAR etch + molybdenum deposition can move >$1B of revenue away from Lam Research.
NAND vertical scaling has hit the HAR-etch wall (6-7 micron / 70:1 channel holes; ~40nm minimum cell thickness). Two manufacturing changes threaten Lam's crown-jewel etch dominance: cryogenic etch (etching at very low temperature to push depth/aspect ratio further, where TEL is strong) and a tungsten-to-molybdenum wordline material change (lower resistance, thinner, enabling more layers). SemiAnalysis frames both as >$1B of share potentially changing hands — a rare crack in one of WFE's tightest oligopolies.
“a potential big shift in market share from Lam Research to Tokyo Electron (TEL) due to two manufacturing changes representing over $1 billion of revenues potentially changing hands.”— NAND Flash Monopoly Broken? Tokyo Electron Moly Dep + Cryo Etch Takes On Lam Research (2023-07-16), SemiAnalysis
6. Nanoimprint lithography will NOT replace EUV — the mask lasts ~50 wafers vs. 100,000+ for a photomask, and defectivity kills the economics.
On paper NIL is seductive: a 4-cell tool costs ~1/10th of an EUV scanner, ~1/4 the cost-per-wafer, ~90% less power, and can theoretically match EUV resolution with no stochastics. In practice the nanometer-scale 3D stamp is fragile — Canon's templates last ~50 wafers (customers dispute Canon's higher claims), and any repeater defect is copied to every field, so inspecting every template would consume 'roughly the entire annual output of mask-inspection tools worldwide.' Kioxia and Micron, who WANT it to work, keep repeating the same complaints. Its real use is niches (metalenses, MEMS). Note the export-control gap: a Japan-sold NIL tool could be re-exported to China.
“How long does that stamp last? Right now, about 50 wafers... Compare that to a photolithography mask which has a lifetime of well over 100,000 wafers.”— Nanoimprint Lithography: Stop Saying It Will Replace EUV (2025-10-26), SemiAnalysis
7. Metal-oxide resist's time has finally come — and it arrives bundled with High-NA at ~A10, not because the industry chose it but because thin-film physics forces it.
High-NA's depth of focus shrinks with the square of NA, forcing very thin resist. Organic CAR resist that thin lacks etch resistance to survive pattern transfer; metal-oxide resist (MOR) has far better etch selectivity plus better resolution-LER-sensitivity. The crossover is ~30nm-pitch vias, ~2 nodes out at A10 — the same point SemiAnalysis models High-NA becoming economical. Most SPIE 2025 High-NA data already used MOR over CAR. A parallel war rages over wet (TEL spin-coat) vs dry (Lam CVD) application of that resist, with winners now emerging in research.
“It will probably make sense to adopt MOR at the same time as high-NA for a small number of critical layers like metals and vias. Most SPIE papers this year with high-NA exposure data used MOR rather than CAR.”— High-NA is Here (for R&D), EUV Cost, Pattern Shaping Gaining Share... (2025-04-14), SemiAnalysis
8. ASML's own long-term guidance is questionable — its 20 High-NA tools/year by 2028 target is 'impossible,' and its wafer model bakes in 10-20% 'inefficient' capacity.
SemiAnalysis repeatedly pokes holes in first-party equipment guidance. ASML's investor-day math assumed 600 DUV + 90 EUV tools/year by 2025 and 20 High-NA/year by 2028 — the last of which they call flatly impossible given the cost problem. ASML's demand model leans on 'technological sovereignty' regionalization adding ~10% inefficient capacity (rising to ~20% of incremental 2025-30 wafers), which would drag utilization toward ~72%. Their fab-count slide got 'a 4 out of 10.' The takeaway: buy-side/sell-side that just plug ASML's guidance are ignoring a large long-term risk.
“the most lofty, and in our view, impossible to hit target of theirs is the plan to have 20 High-NA EUV tool annual shipments by 2028.”— ASML Dilemma: High-NA EUV is Worse vs Low-NA EUV Multi-Patterning (2023-12-11), SemiAnalysis
9. Export controls have gaping holes: DUV, photoresist, components and service — not just EUV — must be blocked, or China rebuilds 7nm from existing tools.
The 2023 trilateral (US/Japan/Netherlands) deal was 'extremely limited,' covering mainly ArFi tools. But SAQP with ArFi (k1=0.391) reaches 5nm-class 28nm minimum-metal-pitch, and even dry-ArF or advanced-KrF can reach 7nm/14nm pitches at ~19% higher wafer cost — trivial for a state subsidizing at nuclear-plant scale. SMIC alone has 100+ DUV tools and could reach >100k wafers/month of 7nm. The un-restricted photoresist supply chain (~75% Japanese) and tool service/parts are the biggest holes: any nation can be cut off from all lithography if Japan restricts resist. Separately, ASML declared it 'can continue to ship all non-EUV systems to China.'
“As a European-based company with limited US technology in our systems, ASML can continue to ship all non-EUV lithography systems to China out of the Netherlands.”— The Gaps In The New China Lithography Restrictions (2023-01-29), SemiAnalysis
10. Batch ALD is a hidden monopoly niche: Kokusai Electric owns ~70% of batch ALD, wins critical 3D NAND deposition at all top-5 makers, and its intensity rises with GAA.
WFE isn't one market — it's dozens of niches each with a hidden leader. Kokusai (KKR-owned, IPO'd 2023) holds ~70% of batch ALD (~46% of all batch deposition), and is the process-of-record for 3D NAND's blocking oxide, charge-trap nitride and tunnel oxide at ALL top-5 NAND makers. AMAT tried to buy it for $2.2B, raised the offer 59% to $3.5B, then aborted after two years awaiting China antitrust approval — an endorsement of the moat. Batch beats single-wafer above 64-layer NAND (depth loading flips the throughput math), and GAA needs several more ALD steps, so KE's TAM structurally grows; TSMC is already its 2nd-largest customer.
“KE dominates the batch ALD process with ~70% market share... For the blocking oxide, charge trap nitride and tunnel oxide, KE's batch ALD is the process tool of record among ALL of the top 5 NAND players.”— Going Vertical: Gate All Around, 3D DRAM, 3D NAND - Kokusai Electric IPO (2023-10-15), SemiAnalysis
11. Fixed costs are exploding — a 3nm mask set approaches $40M — which paradoxically drives MORE equipment demand at trailing nodes as designs proliferate.
Mask-set cost scales far faster than wafer cost: ~$100Ks at 90-45nm, >$1M at 28nm, >$10M at 7nm, ~$40M at 3nm. Combined with soaring verification/validation cost (Intel needed 12 steppings for Sapphire Rapids), only high-volume designs can amortize leading-edge economics — culling AI-chip startups. The flip side, per ASML, is a 40%+ increase in >28nm mask-set starts (48% per eBeam Initiative): not old chips, but NEW designs on mature nodes. That, plus regionalization, is what keeps trailing-edge DUV, deposition and etch demand — and Nikon/Canon/SMEE competition — structurally alive.
“At 28nm it moves beyond $1M. With 7nm, the cost increases beyond $10M, and now, as we cross the 3nm barrier, mask sets will begin to push into the $40M range.”— The Dark Side Of The Semiconductor Design Renaissance (2022-07-24), SemiAnalysis
12. AI is coming for metrology capex: virtual/inline AI process control (e.g. Lynceus) can cut defect-detection time 90% and metrology sampling 4x.
Metrology/inspection is pure overhead — floorspace and cycle time that doesn't advance the wafer — yet indispensable: a 2,000-step process at ~99.98% yield per step (~194 ppm defects, well short of true six-sigma's 3.4 DPMO / ~99.3% cumulative) still compounds to only ~0.678 die yield (~a third of die defective), and one undetected excursion cost TSMC $550M in 2019. Lynceus feeds tool FDC/test data into AI models to predict quality inline, achieving (in two HVM fabs) a 90% cut in time-to-detect (4 days to 3 hours) and a 4x reduction in metrology/inspection sampling. The structural implication: AI virtual metrology is a headwind to the KLA/Onto/Nova sampling-capex growth story even as complexity rises.
“The results are astounding with a 90% reduction in time to detect a defect from 4 days to 3 hours. Furthermore, they were able to achieve a 4x reduction in metrology and inspection sampling frequency.”— Lynceus: Inline, Real-time, AI Based Process Control Monitoring (2022-07-28), SemiAnalysis

Article Deep-Dives

ASML Dilemma: High-NA EUV is Worse vs Low-NA EUV Multi-Patterning (2023-12-11)
The keystone contrarian piece (co-authored by an ex-ASML analyst). Builds a bottom-up litho-cost model proving High-NA single-patterning is MORE expensive than low-NA double-patterning from 3nm through 1nm, because dose rises exponentially with shrinking CD and low-NA runs at full stage-limited throughput. Documents how ASML quietly shifted its own marketing from 'lower cost' (2020) to merely 'less complex' (2021+) — and calls the 20-High-NA-tools-by-2028 target impossible. Places natural High-NA insertion at 2030+ (1nm/7A), when scaling shifts from shrinking to stacking and CD stops falling.
EUV Requirements Halved? Applied Materials' Sculpta Redefines Lithography And Patterning (2023-03-06)
Deep dive on AMAT's Centura Sculpta 'pattern shaping' — an angled ribbon-beam plasma etch that elongates features on one axis to replace a second litho pass. Explains the three use cases (tight corner-to-corner vias, narrow tip-to-tip trenches, >90% stochastic-defect repair), the metal-interconnect insertion at a 2nm-class node in 2024-25, and quantifies a potential ~$4.5B EUV-demand reduction. Rebuts the finance/industry dismissal that it's 'just fancy RIE' — noting AMAT published since 2015 with a first customer since ~2017. Maps ramifications across ASML, Lam, TEL, JSR, KLA, Onto and the resist/mask supply chain.
Going Vertical: Gate All Around, 3D DRAM, 3D NAND - Kokusai Electric IPO (2023-10-15)
The definitive map of the deposition landscape, framed around the Kokusai Electric IPO. Explains ALD's self-limiting conformality, why batch (Kokusai ~70%) beats single-wafer above 64-layer NAND (depth loading), and where each vendor (Kokusai, ASMI, TEL, AMAT, Lam) wins in 3D NAND, DRAM capacitors and GAA. Key structural call: GAA and 3D DRAM sharply raise ALD/etch intensity while cutting litho intensity — the value migration thesis in one company. AMAT tried to buy Kokusai for $2.2B, raised the offer 59% to $3.5B, then aborted after two years awaiting China antitrust approval; TSMC is its 2nd-largest customer.
NAND Flash Monopoly Broken? Tokyo Electron Moly Dep + Cryo Etch Takes On Lam Research (2023-07-16)
Maps the four avenues of NAND scaling (logical/vertical/lateral/architectural) and shows most are tapped out, leaving HAR etch and deposition as the battleground. Two manufacturing shifts — TEL's cryogenic etch and a tungsten-to-molybdenum wordline change — threaten to move >$1B from Lam. Also delivers the memory-cycle call: 2023-24 a NAND glut (utilization ~60%, worst since 1997) setting up a 2025 shortage, with YMTC cut off by export controls removing China's counter-cyclical buffer.
High-NA is Here (for R&D), EUV Cost, Pattern Shaping Gaining Share, Metal Oxide & Dry Resist, Hyper-NA (2025-04-14)
The SPIE 2025 field report — the freshest read on the roadmap. Intel ran 30,000 wafers on two EXE:5000 tools with source power at 110% of target and 0.6nm overlay, declaring both 'in production' (running proven processes, not commercial products). IBM's cost talk confirmed SemiAnalysis's model: High-NA single exposure ~2.5x a low-NA one, only winning vs 3+ masks. Metal-oxide resist arrives with High-NA at ~A10; the wet(TEL) vs dry(Lam) resist war and pattern shaping (Sculpta / TEL Acrevia) gain share; ASML pushes the 6x12" mask to 'early next decade' and teases hyper-NA for the CFET era.
Nanoimprint Lithography: Stop Saying It Will Replace EUV (2025-10-26)
A definitive myth-buster on Canon's J-FIL nanoimprint. On paper NIL wins on cost (~1/10 tool price, ~1/4 cost/wafer, ~90% less power) and resolution. In practice the fragile nanometer-scale stamp lasts ~50 wafers (vs >100,000 for a photomask), every repeater defect prints to every field, and inspecting every template would consume nearly the entire world's mask-inspection output. Kioxia and Micron — who want it to work — keep repeating defect/lifetime/cost complaints. Real use is niches (metalenses, MEMS). Flags a serious export-control gap: a Japan-sold NIL tool can be re-exported to China, potentially handing EUV-level capability to SMIC/Huawei.

Reference: Value Chain

Lithography (patterning)ASML (EUV monopoly + DUV leader), Nikon, Canon (DUV/nanoimprint), SMEE (China) — Prints the circuit pattern. ASML's EUV/High-NA is the single hardest bottleneck; ~35% of a 3nm node's cost. Nikon/Canon relegated to DUV; Canon's nanoimprint bet 'was the wrong bet.'
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Deposition (add material)Applied Materials, Lam Research, Tokyo Electron, ASM International (ALD), Kokusai Electric (batch ALD ~70%) — Lays down films (CVD/PVD/ALD/electroplating). ALD intensity rises hard with GAA and 3D — self-limiting, conformal, but slow, so memory batches it. Kokusai is the batch-ALD specialist; TSMC is its 2nd-largest customer.
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Etch (remove material)Lam Research (HAR etch leader), Tokyo Electron (cryo etch challenger), Applied Materials — Carves patterns/holes. The engine of 3D NAND vertical scaling (70:1 channel holes). Lam dominates HAR; TEL's cryogenic etch + moly deposition could move >$1B of NAND revenue.
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Photoresist track & materialsTokyo Electron (100% EUV coat/develop track), JSR/Inpria, TOK, Shin-Etsu, Lam (dry resist) — Coats, bakes and develops resist around every ASML tool — a $5B+ run-rate monopoly for TEL that pulls in adjacent etch/clean wins. Lam's dry resist is the disruptor; JSR bought Inpria for $514M to defend MOR.
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Process controlKLA (dominant), Onto Innovation, Nova, Lasertec (EUV mask/actinic inspection), Lynceus (AI software) — Metrology and defect inspection to protect yield across 1000+ steps. KLA is the toll-booth; Lasertec monopolizes actinic EUV mask inspection; AI/virtual metrology threatens to shrink the sampling capex.
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Masks / mask equipmentHoya (~80% EUV blanks), AGC/Asahi, Veeco (blank deposition tools), IMS/JEOL (multibeam writers), Photronics — Makes the reticles that carry each layer's pattern; mask sets now approach $40M at 3nm. Veeco monopolizes EUV mask-blank Mo/Si/Ru deposition. A '6x12 inch' larger mask is the swing factor for High-NA economics.
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Specialty / niche toolsVeeco (laser anneal, GaN MOCVD, wet), EV Group (wafer bonders), BE Semi (hybrid bonding), Entegris (materials) — Adjacent enablers: hybrid bonding for CMOS-bonded-array NAND and backside power; laser annealing for GAA dopant activation; wafer bonding for heterogeneous integration. Small TAMs but structurally growing with 3D.

Reference: Core Concepts

WFE (Wafer Fabrication Equipment). The front-end toolset that turns bare silicon into patterned chips: lithography, deposition, etch, CMP, ion implant, and process control (metrology/inspection). A ~$100B/year market segmented by step, each step an oligopoly.

EUV / High-NA EUV. Extreme ultraviolet lithography at 13.5nm wavelength — ASML monopoly. High-NA (0.55 aperture, EXE:5000) images smaller features but halves the exposure field, so large dies exceeding the half-field may require stitching, while smaller dies do not. The critical debate: is it worth ~2x the cost?

Multi-patterning (LELE/SADP/SALELE). Using multiple exposures + etch/deposition to print features finer than one exposure allows. Doubles/triples litho cost but keeps each exposure at a cheaper, lower-dose/easier-imaging point on the exponential dose-vs-CD curve.

Pattern shaping (AMAT Sculpta). A directional (angled ribbon-beam plasma) etch that elongates features in one axis after a single exposure, replacing a second litho pass. Can remove EUV double-patterning on some layers; ~$4.5B potential EUV demand reduction.

DSA (Directed Self-Assembly). Block copolymers (PS-b-PMMA) that self-organize into ~9-20nm lines guided by a coarse EUV template. 'Heals' line-edge roughness, letting EUV run at 50%+ lower dose — Intel's proposed 'magic bullet' to make High-NA economical at 14A.

CAR vs MOR vs Dry Resist. Photoresist platforms. CAR (organic; resist from JSR/TOK/Shin-Etsu, run on TEL's incumbent coat/develop track); MOR (metal-oxide, Inpria/JSR, better etch selectivity for thin High-NA films); Dry resist (Lam CVD-deposited metal, ~2x throughput, ~50% dose cut). A $5B+ battle.

ALD & Batch vs Single-Wafer. Atomic Layer Deposition deposits material through self-limiting cyclic surface reactions, typically Å-scale, sub-monolayer growth per cycle — highest conformality for high-aspect-ratio 3D structures. Batch (Kokusai ~70% share) processes 100s of wafers for memory; single-wafer (ASMI/AMAT/Lam) for precise logic films.

HAR Etch (High Aspect Ratio). Etching channel holes 70x deeper than wide through 3D NAND stacks (>250 layers, ~7 microns). Lam's crown jewel; Tokyo Electron's cryogenic etch threatens >$1B of it. The gating step for NAND vertical scaling.

Process Control (Metrology/Inspection). Measuring/inspecting wafers between steps to catch defects before yield is destroyed (a single fab excursion cost TSMC $550M in 2019). KLA-dominated; ~10-15% of WFE. AI (e.g. Lynceus) aims to cut this capex via virtual metrology.

Open Questions

Sources (SemiAnalysis)

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